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DATA SHEET
SAA6752HS MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
Product specification Supersedes data of 2002 Apr 09 2002 Dec 09
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
CONTENTS 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2 2.1 2.2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 FEATURES Video input and preprocessing Video compression Audio input Audio compression Stream multiplexer Output interface Control domain Other features GENERAL DESCRIPTION General Application fields QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION System operation Digital video input Video compression Digital audio input Audio compression SDRAM interface Multiplexer MPEG stream output port Clock generation Power control and reset I2C-bus interface Exception handling 15 16 17 18 8 8.1 8.2 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5
SAA6752HS
BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes I2C-BUS CONTROL AND STATUS REGISTERS LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2002 Dec 09
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
1 1.1 FEATURES Video input and preprocessing
SAA6752HS
* Digital YUV input according to "ITU-R BT.656" (8 bits at 27 MHz) and "ITU-R BT.601" * Support of enhanced "ITU-R BT.656" input format containing decoded VBI data readable via I2C-bus; Closed Caption (CC), Wide Screen Signalling (WSS) and copyright information with Copy Generation Management System (CGMS) * Processing of non-broadcast video signals from analog VCR according to IEC 756 * Two video clock input pins for switching two digital video sources * "ITU-R BT.601" format conversion to 1/2D1, 2/3D1 and Standard Interchange Format (SIF) * 4 : 2 : 2 to 4 : 2 : 0 colour format conversion * Decimation filtering for all format conversions * Adaptive median filter and motion compensated filter for input noise reduction. 1.2 Video compression
1.3
Audio input
* Audio inputs: I2S format or EIAJ format (16, 18 or 20 bits), master or slave mode at 32, 44.1 and 48 kHz * Two digital I2S input ports for selection between two digital audio sources * Audio clock generation: 256fs or 384fs (where fs = 48 kHz) locked to video frame rate (if video is present and locking is enabled) * Sample rate conversion to 48 kHz (locked to video frame rate if enabled) for slave mode operation in all modes except Digital Versatile Disc (DVD) compliant bypass. 1.4 Audio compression
* Real-time MPEG-2 encoding compliant to Main Profile at Main Level (MP@ML) for 625 and 525 interlaced line systems * Supported resolutions: D1, 2/3D1, 1/2D1 and SIF * IPB frame, IP frame and I frame only encoding supported at all modes * Supported bit rates: up to 25 Mbit/s I-only encoding; up to 15 Mbit/s IP-only or IBP encoding. * Variable video bit rate mode for constant picture quality and constant bit rate mode to gain optimum picture quality from a fixed channel transfer rate * Access to bit rate control parameters whilst encoding to support external real-time control algorithms (e.g. constrained variable bit rate control) * Programmable Group Of Pictures (GOP) structure * Innovative motion estimation with wide search range * Adaptive quantization * Motion compensated noise filter.
* Dolby(R)(1) Digital Consumer Encoding (DDCE) also known as AC-3(2) 2 channel audio encoding at 256 kbit/s or 384 kbit/s (only for SAA6752HS/V101 and SAA6752HS/V103) * MPEG-1 layer 2 audio encoding at 256 kbit/s or 384 kbit/s * Input data bypass for Linear Pulse Code Modulation (LPCM) and compressed audio data [MPEG-1, MPEG-2, Dolby(R) Digital (DD) and Digital Theatre System (DTS)] according to IEC 61937 * Preamble Pc, Preamble Pd and bit stream information captured for identification of modes during bypass of compressed audio data for MPEG-1, MPEG-2, DD and DTS according to IEC 61937 * Audio mute via I2C-bus control for all modes except DVD-compliant bypass.
(1) Dolby is a registered trademark of Dolby Laboratories Licensing Corporation. (2) AC-3 is a registered trademark of Dolby Laboratories Licensing Corporation.
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
1.5 Stream multiplexer 2 2.1 GENERAL DESCRIPTION General
SAA6752HS
* Multiplexing of video and audio streams according to the MPEG-2 systems standard ("ISO 13818-1") * Generation and output of MPEG-2 Transport Streams (TS), MPEG-2 Program Streams (PS), Packetized Elementary Streams (PES) and Elementary Streams (ES) compliant to the DVD, D-VHS and DVB standards * MPEG time stamp (PTS/DTS/SCR/PCR) generation and insertion (synchronization) * Insertion of metadata * Optional generation of empty time slots for subsequent insertion of application specific data packets * Optional insertion of user data in the GOP header and in the picture header * Optional automatic insertion of Closed Caption data according to DVD or ATSC standard (only for SAA6752HS/V103) * Optional generation of transport streams with variable bit rate (only for SAA6752HS/V103). 1.6 Output interface
Philips Semiconductors' second generation real time MPEG-2 encoder, the SAA6752HS, is a highly integrated single-chip audio and video encoding solution with flexible multiplexing functionality. With our expertise in two critical areas for consumer video encoding, noise filtering and motion estimation, we have pushed the boundaries for video quality even further, providing enhanced quality for low bit rates and enabling increased recording times for a given storage capacity. The SAA6752HS will also enable a key driver for new consumer digital recording applications and system cost reduction. By integrating all audio encoding and multiplexing functionality we will be moving from a three chip to a one chip system, with cost efficient design and process technology, thus providing a truly low cost, high quality encoding system. The SAA6752HS/V102 is intended for customers whose application does not require the DDCE function. The SAA6752HS gives significant advantages to customers developing digital recording applications: * Fast time-to-market and low development resources. By adding a simple external video input processor IC, an audio analog-to-digital converter, and an external SDRAM, analog video and audio sources are compressed into high quality MPEG-2 video and MPEG-1 layer 2 or AC-3 audio streams, multiplexed into a single program or transport stream for simple connection to various storage media or broadcast media. Hence, making design effort for our customers a minimum, as well as removing the need for in-depth experience in MPEG encoding. * Low system host resources. All video and audio encoding algorithms and software are run on an internal MIPS(R)(1) processor. The SAA6752HS only requires a small amount of communication from the system host processor to set up and control required encoding parameters via the I2C-bus.
* Parallel interface 8-bit master/slave output * 3-state output port * Glueless interfacing with IEEE 1394 chip sets (for example, PDI 1394 L11) * Data Expansion Bus Interface (DEBI) interface. 1.7 Control domain
* All control done via I2C-bus * I2C-bus slave transceiver up to 400 kbit/s * I2C-bus slave address select pin * Host interrupt flag pin. 1.8 Other features
* Single external clock or single crystal 27 MHz * Separate 27 MHz system clock output * Interface voltage 3.3 V * TTL compatible digital outputs * Power supply voltage 3.3 and 2.5 V * Boundary Scan Test (BST) supported * Power-down mode * Single SDRAM system memory (16 Mbit@16 bit or 64 Mbit@16 bit).
(1) MIPS is a registered trademark of MIPS Technologies.
2002 Dec 09
4
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
2.2 2.2.1 Application fields DVD BASED OPTICAL DISC RECORDERS (DVD+RW, DVD-RW, DVD-RAM) 2.2.3
SAA6752HS
DIGITAL VCR (DVHS) RECORDING
Emerging optical disc based recording systems target to replace the existing consumer recording (VCR) and playback (DVD and VCD) products. The first generation recordable DVD based products will want to maximise recording times for the 4.7 Gbyte storage capacity. For these systems the SAA6752HS is critical, with its superior noise filtering and motion estimation, in enabling high quality at low bit rates. Playback compatibility with existing DVD decoding solutions will also be important, which is why the SAA6752HS provides Dolby(R) digital consumer (AC-3) audio encoding to allow playback through existing players implementing DDCE (AC-3) decoding dominant in current DVD platforms. The DVD stream is based on MPEG Program Stream (PS). The SAA6752HS directly outputs MPEG PS compliant to the DVD standard. 2.2.2 HDD BASED TIME SHIFT RECORDING
A DVHS player records streams based on MPEG Transport Streams (TS) packed in logical tape tracks. The SAA6752HS output streams are compliant with DVHS standard requirements. 2.2.4 VIDEO EDITING/TRANSMISSION/SURVEILLANCE/
CONFERENCING
The SAA6752HS can operate as a stand-alone device in all the above applications. The SAA6752HS full features and flexibility allows customers to tailor functionality and performance to specific application requirements. All required control settings such as GOP size and bit rate modes can be selected via the I2C-bus.
Hard Disc Drive (HDD) based time-shift systems enable Personalized TV (PTV) functionality, providing consumers with new powers of control over what and when to watch broadcast content. With the audio and video content recorded digitally, identification, search and retrieval becomes a `no brainer' task as compared to traditional VCR functionality. Combine this with electronic program guides and intelligent control, and the PTV can also analyse the viewers watching habits to search for programs likely to be of interest and automatically recorded in anticipation of the viewers preferences. Since HDD recorders are closed systems, the recording format stream can be proprietary. The SAA6752HS flexible multiplexing formats support a number of recording stream formats for HDD including MPEG Transport Stream (TS) or MPEG Packetized Elementary Stream (PES).
2002 Dec 09
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
3 QUICK REFERENCE DATA PARAMETER digital supply voltage (pad cells) digital supply voltage (core) total analog plus digital supply current total power dissipation SDRAM clock frequency I2C-bus input clock frequency output bit-rate HIGH-level digital input voltage LOW-level digital input voltage HIGH-level digital output voltage LOW-level digital output voltage ambient temperature 3.0 2.3 407 0.95 10-6)] - 100 1.5 1.7 -0.5 VDDP - 0.4 0 0 MIN. TYP. 3.3 2.5 2.5 453 27 108 - - - - - - - 3.6 2.7 2.7 525
SAA6752HS
SYMBOL VDDP VDDCO VDDA IDD(tot) Ptot fDCXO fSDRAM fSCL B VIH VIL VOH VOL Tamb 4
MAX.
UNIT V V V mA W 10-6)] MHz MHz kHz Mbit/s V V V V C
analog supply voltage (oscillator and PLL) 2.3
1.16 1.48 27 x [1 + (200 x - 400 25 3.6 +0.7 VDDP 0.4 70
quartz frequency (digital controlled tuning) 27 x [1 - (200 x
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION SOT316-1
SAA6752HS/V101(1) SQFP208 plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height SAA6752HS/V102(2) SAA6752HS/V103(3) Notes 1. MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer. 2. MPEG-2 video and MPEG-audio encoder with multiplexer, but without AC-3 audio encoder.
3. MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer and automatic user data insertion.
2002 Dec 09
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2002 Dec 09
system clock reference
5
Philips Semiconductors
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
BLOCK DIAGRAM
SDRAM 16 Mbit @ 16-bit or 64 Mbit @ 16-bit
system clock output
audio clock
SAA6752HS
digital video input VIDEO FRONT-END RAM ROM
SDRAM-INTERFACE STREAM DOMAIN SCHEDULER
SYSTEM CLOCK REFERENCE
CLOCK
27 MHz
external clock
digital audio input
AUDIO INTERFACE
AUDIO COMPRESSION
VIDEO COMPRESSION
STREAM MULTIPEXER
OUTPUT INTERFACE
MPEG output
7
PI-bus I 2C-BUS GPIO RESET CONTROL MIPS (R) CPU STATIC MEM RAM ROM TAP DEBUG ONLY
MHC128
I 2C-bus
host interrupt
reset
boundary scan
SAA6752HS
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
6 PINNING SYMBOL VSSP SDATA1 SCLK1 SWS1 VDDP SDATA2 SCLK2 SWS2 ACLK VSSP IDQ YUV0 YUV1 YUV2 YUV3 YUV4 YUV5 YUV6 YUV7 VSSP HSYNC VSYNC FID VCLK1 VSSCO VSSCO VDDCO VDDCO VDDP VCLK2 PDOAV PDIDS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 INPUT/OUTPUT(1) ground input input/output input/output supply input/output input/output input/output output ground input input input input input input input input input ground input input input input ground ground supply supply supply input 3-state output input Imax (mA) - - 4 4 - 4 4 4 4 - - - - - - - - - - - - - - - - - - - - - 4 - pad ground DESCRIPTION
SAA6752HS
I2S-bus serial data input port 1 with internal pull-down resistor I2S-bus serial clock port 1 with internal pull-down resistor I2S-bus word select port 1 with internal pull-down resistor pad ring supply voltage (3.3 V) I2S-bus serial data port 2 with internal pull-down resistor I2S-bus serial clock port 2 with internal pull-down resistor I2S-bus word select port 2 with internal pull-down resistor audio clock output (256fs or 384fs) pad ground reserved input with internal pull-down resistor; (recommended to connect to pin VSSP) video input signal bit 0 (LSB) video input signal bit 1 video input signal bit 2 video input signal bit 3 video input signal bit 4 video input signal bit 5 video input signal bit 6 video input signal bit 7 (MSB) pad ground horizontal sync input (video) with internal pull-down resistor vertical sync input (video) with internal pull-down resistor video field identification input (odd/even field) with internal pull-down resistor video clock input 1 (27 MHz) with internal pull-down resistor core ground core ground core supply voltage (2.5 V) core supply voltage (2.5 V) pad ring supply voltage (3.3 V) video clock input 2 (27 MHz) with internal pull-down resistor parallel stream data output for audio/video identifier parallel stream data input for data strobe [request for packet in Data Expansion Bus Interface (DEBI) slave mode] with internal pull-up resistor parallel stream data output for packet sync pad ground parallel stream data valid output with internal pull-up resistor parallel stream data output bit 0 (LSB) 8
PDOSYNC VSSP PDOVAL PDO0 2002 Dec 09
33 34 35 36
3-state output ground 3-state output 3-state output
4 - 4 4
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SYMBOL PDO1 PDO2 VDDP PDO3 PDO4 PDO5 PDO6 VSSP PDO7 PDIOCLK I2CADDRSEL SD_DQ15 VDDP SD_DQ0 SD_DQ14 SD_DQ1 VSSP SD_DQ13 SD_DQ2 SD_DQ12 VDDP SD_DQ3 SD_DQ11 SD_DQ4 SD_DQ10 VSSP SD_DQ5 SD_DQ9 SD_DQ6 SD_DQ8 VDDP SD_DQ7 SD_DQM1 SD_DQM0 SD_WE VSSP SD_CAS SD_CLK SD_RAS SD_CKE 2002 Dec 09 PIN 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 INPUT/OUTPUT(1) 3-state output 3-state output supply 3-state output 3-state output 3-state output 3-state output ground 3-state output input/output input input/output supply input/output input/output input/output ground input/output input/output input/output supply input/output input/output input/output input/output ground input/output input/output input/output input/output supply input/output output output output ground output output output output Imax (mA) 4 4 - 4 4 4 4 - 4 4 - 8 - 8 8 8 - 8 8 8 - 8 8 8 8 - 8 8 8 8 - 8 8 8 8 - 8 8 8 8 DESCRIPTION parallel stream data output bit 1 parallel stream data output bit 2 pad ring supply voltage (3.3 V) parallel stream data output bit 3 parallel stream data output bit 4 parallel stream data output bit 5 parallel stream data output bit 6 pad ground parallel stream data output bit 7 (MSB) parallel stream clock input/output
SAA6752HS
I2C-bus address select input with internal pull-up resistor SDRAM data input/output bit 15 (MSB) pad ring supply voltage (3.3 V) SDRAM data input/output bit 0 (LSB) SDRAM data input/output bit 14 SDRAM data input/output bit 1 pad ground SDRAM data input/output bit 13 SDRAM data input/output bit 2 SDRAM data input/output bit 12 pad ring supply voltage (3.3 V) SDRAM data input/output bit 3 SDRAM data input/output bit 11 SDRAM data input/output bit 4 SDRAM data input/output bit 10 pad ground SDRAM data input/output bit 5 SDRAM data input/output bit 9 SDRAM data input/output bit 6 SDRAM data input/output bit 8 pad ring supply voltage (3.3 V) SDRAM data input/output bit 7 SDRAM data mask enable output bit 1 SDRAM data mask enable output bit 0 (LSB) SDRAM write enable output (active LOW) pad ground SDRAM column address strobe output (active LOW) SDRAM clock output SDRAM row address strobe output (active LOW) SDRAM clock enable output 9
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SYMBOL VSSCO VSSCO VDDCO VDDCO VDDP SD_CS SD_A13 SD_A9 SD_A8 VSSP SD_A11 SD_A7 SD_A12 SD_A6 VDDP SD_A10 SD_A5 SD_A0 SD_A4 VSSP SD_A1 SD_A3 SD_A2 SD_DQM3 VDDP SD_DQM2 SD_DQ31 SD_DQ16 VSSP SD_DQ30 SD_DQ17 SD_DQ29 VDDP SD_DQ18 SD_DQ28 SD_DQ19 SD_DQ27 VSSP SD_DQ20 SD_DQ26 2002 Dec 09 PIN 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 INPUT/OUTPUT(1) ground ground supply supply supply output output output output ground output output output output supply output output output output ground output output output output supply output input/output input/output ground input/output input/output input/output supply input/output input/output input/output input/output ground input/output input/output Imax (mA) - - - - - 8 8 8 8 - 8 8 8 8 - 8 8 8 8 - 8 8 8 8 - 8 8 8 - 8 8 8 - 8 8 8 8 - 8 8 core ground core and substrate ground core supply voltage (2.5 V) core supply voltage (2.5 V) pad ring supply voltage (3.3 V) SDRAM chip select output (active LOW) DESCRIPTION
SAA6752HS
SDRAM address output bit 13 (bank selection for 64 Mbit) SDRAM address output bit 9 SDRAM address output bit 8 pad ground SDRAM address output bit 11 (bank selection for 16 Mbit) SDRAM address output bit 7 SDRAM address output bit 12 (bank selection for 64 Mbit) SDRAM address output bit 6 pad ring supply voltage (3.3 V) SDRAM address output bit 10 SDRAM address output bit 5 SDRAM address output bit 0 (LSB) SDRAM address output bit 4 pad ground SDRAM address output bit 1 SDRAM address output bit 3 SDRAM address output bit 2 reserved (do not connect) pad ring supply voltage (3.3 V) reserved (do not connect) reserved (do not connect) reserved (do not connect) pad ground reserved (do not connect) reserved (do not connect) reserved (do not connect) pad ring supply voltage (3.3 V) reserved (do not connect) reserved (do not connect) reserved (do not connect) reserved (do not connect) pad ground reserved (do not connect) reserved (do not connect) 10
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SYMBOL SD_DQ21 SD_DQ25 VDDP SD_DQ22 SD_DQ24 SD_DQ23 EXTCLK VSSP VSSA XTALI XTALO VDDA VSSCO VSSCO VDDCO VDDCO VDDP TDI TMS TCK TDO VSSP TRST CLKOUT TEST0 TEST1 VDDP TEST2 SDA SCL RESET VSSP RTS PIN 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 INPUT/OUTPUT(1) input/output input/output supply input/output input/output input/output input ground ground analog input analog output supply ground ground supply supply supply input input input 3-state output ground input output input/output input/output supply input/output input/open-drain output input/open-drain output input ground output Imax (mA) 8 8 - 8 8 8 - - - - - - - - - - - - - - 4 - - 4 4 4 - 4 - - - - 4 DESCRIPTION reserved (do not connect) reserved (do not connect) pad ring supply voltage (3.3 V) reserved (do not connect) reserved (do not connect) reserved (do not connect)
SAA6752HS
27 MHz external clock input with internal pull-up resistor pad ground oscillator analog ground crystal oscillator input (27 MHz); note 2 crystal oscillator output (27 MHz) oscillator analog supply voltage (2.5 V) core ground core ground core supply voltage (2.5 V) core supply voltage (2.5 V) pad ring supply voltage (3.3 V) boundary scan test data input; pin must float or set to HIGH during normal operating; with internal pull-up resistor; note 3 boundary scan test mode select; pin must float or set to HIGH during normal operating; with internal pull-up resistor; note 3 boundary scan test clock; pin must be set to LOW during normal operating; with internal pull-up resistor; note 3 boundary scan test data output; pin not active during normal operating; with 3-state output; note 3 pad ground test reset input (active LOW), for boundary scan test (with internal pull-up resistor); notes 3 and 4 27 MHz system clock output reserved (do not connect) reserved (do not connect) pad ring supply voltage (3.3 V) reserved (do not connect) I2C-bus serial data input/output I2C-bus serial clock input/output reset input (active LOW); with internal pull-up resistor pad ground reserved (do not connect); Universal Asynchronous Receiver/Transmitter (UART) request to send output (active LOW) 11
2002 Dec 09
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SYMBOL CTS PIN 150 INPUT/OUTPUT(1) input Imax (mA) - DESCRIPTION
SAA6752HS
reserved (recommended connect to pin VDDP); UART clear to send input; external static memory select input (active LOW); with internal pull-up resistor reserved (recommended connect to pin VDDP); UART receive data; internal boot select input; with internal pull-up resistor reserved (do not connect); UART transmit data pad ring supply voltage (3.3 V) reserved (do not connect) reserved (do not connect) host interrupt flag output; with internal pull-up resistor (active LOW) pad ground reserved (do not connect); static memory output enable output (active LOW) reserved (do not connect); static memory address output bit 9 reserved (do not connect); static memory address output bit 10 pad ring supply voltage (3.3 V) reserved (do not connect); static memory address output bit 8 reserved (do not connect); static memory address output bit 11 reserved (do not connect); static memory address output bit 7 reserved (do not connect); static memory address output bit 12 pad ground reserved (do not connect); static memory address output bit 6 reserved (do not connect); static memory address output bit 13 reserved (do not connect); static memory address output bit 5 reserved (do not connect); static memory address output bit 14 pad ring supply voltage (3.3 V) reserved (do not connect); static memory write enable output (active LOW) reserved (do not connect); static memory data input/output bit 7 with internal pull-down resistor reserved (do not connect); static memory data input/output bit 8 with internal pull-down resistor reserved (do not connect); static memory data input/output bit 6 with internal pull-down resistor pad ground reserved (do not connect); static memory data input/output bit 9 with internal pull-down resistor reserved (do not connect); static memory data input/output bit 5 with internal pull-down resistor reserved (do not connect); static memory data input/output bit 10 with internal pull-down resistor
RXD TXD VDDP SM_LB SM_UB H_IRF VSSP SM_OE SM_A9 SM_A10 VDDP SM_A8 SM_A11 SM_A7 SM_A12 VSSP SM_A6 SM_A13 SM_A5 SM_A14 VDDP SM_WE SM_D7 SM_D8 SM_D6 VSSP SM_D9 SM_D5 SM_D10
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179
input output supply input/output input/output 3-state output ground output output output supply output output output output ground output output output output supply output input/output input/output input/output ground input/output input/output input/output
- 4 - 4 4 4 - 4 4 4 - 4 4 4 4 - 4 4 4 4 - 4 4 4 4 - 4 4 4
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SYMBOL SM_D4 VSSCO VSSCO VDDCO VDDCO VDDP SM_D11 SM_D3 SM_D12 SM_D2 VSSP SM_D13 SM_D1 SM_D14 SM_D0 VDDP SM_D15 SM_CS3 SM_A4 SM_A3 VSSP SM_A2 SM_A15 SM_A1 SM_A16 VDDP SM_A0 SM_A17 SM_CS0 PIN 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 INPUT/OUTPUT(1) input/output ground ground supply supply supply input/output input/output input/output input/output ground input/output input/output input/output input/output supply input/output output output output ground output output output output supply output output output Imax (mA) 4 - - - - - 4 4 4 4 - 4 4 4 4 - 4 4 4 4 - 4 4 4 4 - 4 4 4 DESCRIPTION
SAA6752HS
reserved (do not connect); static memory data input/output bit 4 with internal pull-down resistor internal pre-driver and substrate ground core ground core supply voltage (2.5 V) internal pre-driver supply voltage (2.5 V) pad ring supply voltage (3.3 V) reserved (do not connect); static memory data input/output bit 11 with internal pull-down resistor reserved (do not connect); static memory data input/output bit 3 with internal pull-down resistor reserved (do not connect); static memory data input/output bit 12 with internal pull-down resistor reserved (do not connect); static memory data input/output bit 2 with internal pull-down resistor pad ground reserved (do not connect); static memory data input/output bit 13 with internal pull-down resistor reserved (do not connect); static memory data input/output bit 1 with internal pull-down resistor reserved (do not connect); static memory data input/output bit 14 with internal pull-down resistor reserved (do not connect); static memory data input/output bit 0 (LSB) with internal pull-down resistor pad ring supply voltage (3.3 V) reserved (do not connect); static memory data input/output bit 15 (MSB) with internal pull-down resistor reserved (do not connect); static memory chip select output for external ROM or RAM (active LOW) reserved (do not connect); static memory address output bit 4 reserved (do not connect); static memory address output bit 3 pad ground reserved (do not connect); static memory address output bit 2 reserved (do not connect); static memory address output bit 15 reserved (do not connect); static memory address output bit 1 reserved (do not connect); static memory address output bit 16 pad ring supply voltage (3.3 V) reserved (do not connect); static memory address output bit 0 (LSB) reserved (do not connect); static memory address output bit 17 (MSB) reserved (do not connect)
2002 Dec 09
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
Notes
SAA6752HS
1. All input pins, input/output pins (in input mode), output pins (in 3-state mode) and open-drain output pins are limited to 3.3 V. 2. If used with external clock source the input voltage has to be limited to 2.5 V. 3. In accordance with the "IEEE 1149.1" standard. 4. Special function of pin TRST: a) For board designs without boundary scan implementation, pin TRST must be connected to ground. b) Pin TRST provides easy initialization of the internal BST circuit. By applying a LOW level it can be used to force the internal Test Access Port (TAP) controller to the Test-Logic-Reset state (normal operating) immediately.
208
handbook, halfpage
157
1
156
SAA6752HS
52
105
53
104
MHC129
Fig.2 Pin configuration.
2002 Dec 09
14
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7 7.1 7.1.1 FUNCTIONAL DESCRIPTION System operation GENERAL 7.1.2 OPERATING MODES
SAA6752HS
There are five operating modes: 1. Idle. This mode is set after applying a hard reset (i.e. on power-up). In this mode the SAA6752HS can be initialized by the host to the required configuration. Video and audio processing is disabled. A hard reset always resets the SAA6752HS configuration parameters back to the default states. 2. Stop. In Stop mode, the video and audio input processing is enabled but the multiplexer output remains disabled. It is possible to read status information on the input video and audio signals via the I2C-bus. The SAA6752HS initialization settings cannot be modified, except to some specific dynamic encoding parameters (i.e. bit rate setting). 3. Encode. In this mode, the multiplexer output is enabled. Like Stop mode, only dynamic encoding parameters can be modified in this mode. 4. Paused. This mode allows the SAA6752HS to make seamless transitions. Restarting from Paused mode will generate a stream output with sequential time stamps and MPEG buffer model content. 5. Power-down. In this mode, the internal clock is disabled, sending the SAA6752HS into a (non-functional) power saving state. A hard reset will re-initialize the SAA6752HS.
The SAA6752HS has a multi-processor architecture. The different processing and control modules are not locked to each other but run independently within the limits of the global scheduling. The data transfer between the processing units is carried out via FIFO memories or the external SDRAM. The device is configured and the operation modes are selected via the I2C-bus. Compared to the ROM code versions V101 and V102 the following functions have been added in ROM code version V103: * User data can be changed during Encode mode and several user data insertion modes can be selected via subaddress 65H. Two of these modes allow the automatic insertion of Closed Caption user data either compliant to the DVD standard or compliant to the ATSC/NTSC standard * Transport streams with variable bit rate can be generated by discarding the null packets * Insertion of leading null bytes * Forced FID toggle on/off can be selected via I2C-bus * Noise filter parameter can be modified during all modes.
handbook, full pagewidth
power applied HARD RESET RECONFIGURE
SLEEP
RECONFIGURE
STOP
START
Powerdown
Idle
Stop
Encode
Paused
HARD RESET
ENABLE
START
PAUSE
MHC130
START
Fig.3 Mode transition diagram.
2002 Dec 09
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.1.3 MODE TRANSITION COMMANDS
SAA6752HS
The video interface is designed for use with Philips SAA7114 digital multi-standard decoder or similar video decoders. The input interface accepts a digital video input stream according to "ITU-R-BT.601". 625 lines standard at 50 Hz and 720 pixels by 576 lines as well as 525 lines at 60 Hz and 720 pixels by 480 lines are covered. The video synchronization may either follow "ITU-R-BT.656" recommendation or can also be supplied by external signals (HSYNC, VSYNC and FID). The formatter module performs a colour conversion from 4 : 2 : 2 to 4 : 2 : 0 format. Optionally, also SIF progressive downscaling and 2/3D1, 1/2D1 downscaling may be activated. The SAA6752HS supports non-standard features of the SAA711x series of video input processors, such as hard-wired external synchronization signals (2 and 3-wire sync), special VCR playback signal streams (IEC 756 subset for VCR playback and still pictures), extraction of sliced data from the input video stream. 7.2.2 VIDEO FRONT-END CONFIGURATION OPTIONS
There are seven mode transition commands: 1. SOFT RESET. Like a hard reset, a soft reset can be applied in any mode, setting the SAA6752HS back to Idle mode and resetting all configuration parameters back to the default settings. 2. RECONFIGURE. This command sets the SAA6752HS back to Idle mode without resetting the configuration parameters back to the default settings. 3. ENABLE. This transition sets Stop mode, enabling the video and audio input processing. 4. START. This transition sets Encode mode, enabling the multiplexer stream output. Note that if the SAA6752HS is commanded to start from the Idle mode, then the internal transition is via the Stop mode. 5. STOP. This command will disable the multiplexer stream output, setting the SAA6752HS to Stop mode. The current GOP and/or audio frame is completed and an end of sequence bit appended to the stream. 6. PAUSE. A PAUSE transition will cause the multiplexer to complete the current GOP and/or audio frame but no end of sequence bit is appended. The current MPEG buffer model contents are saved to provide a seamless transition on START. 7. SLEEP. This mode disables the internal clock. 8. FORCED RECONFIGURE. A STOP command whilst in the Encode mode will not work in case the video or audio input signal is interrupted, because for stopping, the SAA6752HS tries to finish the current GOP. The forced reconfigure command allows a mode transition back to the Idle state, without losing the actual configuration settings. The SAA6752HS is not able to process any other commands during mode transitions. In this event, a get running mode request will return a busy flag. The completion of a mode transition can also be flagged as an event using the host interrupt pin. 7.2 7.2.1 Digital video input GENERAL
The following configuration options can be selected from the host: * VIDEO INPUT PORT SELECTION. Two input clock pins are selectable. * VIDEO INPUT FORMAT. 525 or 625-line formats can be selected. * VIDEO SYNC FORMAT. Various combinations and polarities of HSYNC, VSYNC and Field Information (FID) can be selected as the source of sync signal processing. * VIDEO FILTER SETTINGS. Noise pre-filter and horizontal filters can be enabled and, if the default coefficients are not suitable for an application, new coefficients can be set. * VIDEO FORMAT CONVERSION. Selection of conversion from D1 to 1/2D1, 2/3D1 or SIF progressive downscaling. * VBI DATA EXTRACTION. VBI data extraction of WSS or CC data can be enabled. 7.2.3 VIDEO ENCODER STATUS INFORMATION
The video front-end processes an "ITU-R BT.601/605" compliant video stream for conversion to 4 : 2 : 0 format (MP@ML). It includes synchronization, digital video signal processing through several filters, subsampling, sliced/raw VBI data handling, and SDRAM address generation.
The following configuration option can be selected from the host: * VBI DATA: WSS and CC data can be read back via the I2C-bus.
2002 Dec 09
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.2.4 DATA INPUT FORMAT
SAA6752HS
Using 2 pin synchronization, the FID information is given by the timing of the transition of the V-sync. If a Vertical Blanking Interval (VBI) starts during H-sync, the next field will be the top field, otherwise it will be the bottom field. A sync filter is used to inhibit sync signal triggering if an incorrect number of pixels or lines has been input. It also checks for the correct consecutive fields. The filter works on three different levels. An H-sync is only accepted after a predefined number of video cycles, a V-sync is only accepted after a programmed number of lines and a field is only accepted if top field follows bottom field or vice versa.
7.2.4.1
Interface definition
The data input interface uses 13 pins, all of which are inputs (see Table 1). Pins YUV0 to YUV7 carry video and synchronization data and 3 pins are reserved for control purposes. Two separate clock inputs allow two different signal sources to be used. The input clock can be asynchronous to the SAA6752HS system clock. Table 1 List of pins data input port PIN YUV0 to YUV7 FID HSYNC VSYNC VCLK1 or VCLK2 Note 1. In ITU-T 656 mode sync signals are embedded in the video data input stream. The external sync signals are not used. 7.2.5 VIDEO SIGNAL PROCESSING DESCRIPTION video input signal (synchronous to VCLK) odd/even field identification signal; note 1 horizontal synchronization signal; note 1 vertical synchronization signal; note 1 video clock signal (from source 1 or 2)
7.2.5.3
Horizontal and vertical shift
This function is intended for correction in synchronization of external sync signals if incorrectly timed. The amount of shift is programmable via the I2C-bus.
7.2.5.4
SAV/EAV decoder
A SAV/EAV decoder extracts the F, V and H bits from the video timing reference code. The decoder evaluates the protection bits to be able to correct one bit errors within the code word. If multiple bit errors are detected, the protection bits are ignored and the field (F), vertical sync (V) and horizontal sync (H) bits are directly extracted from the code.
7.2.5.5
Video format conversion
7.2.5.1
Acquisition of video data
Data is latched with the incoming video clock to provide robust data capture. Video clock and data is unlocked to the internal system clock therefore a clock domain bridge is used. This is performed by oversampling of video clock and data with 108 MHz.
The SAA6752HS converts the input video input signal to the formats defined in Table 2 controlled by the I2C-bus command. A 4 : 2 : 2 to 4 : 2 : 0 colour conversion is performed as this is a pre-requisite of MPEG MP@ML encoding. Table 2 Format conversion MODE PICTURE FORMAT (PIXEL/LINES) 720 480 352; note 1 352; notes 1 and 2
7.2.5.2
Sync decoding and filtering
D1 2/3D1 1/2D1 SIF Notes
To allow selection of the right portion of the video input stream, synchronization signals from the stream are recognized by a sync decoder. This checks the incoming field (FID), vertical sync and horizontal sync. It is possible to select either `internal synchronization' (which means that SAV/EAV codes in the ITU 601/656 video streams are used) or externally applied hardware synchronization signals (which are given by the video input processor). In the latter case, 3 pin or 2 pin (V-sync and H-sync only) synchronization can be used.
1. The 8 pixels at the right edge of the scaled picture are not encoded. 2. Top field only.
2002 Dec 09
17
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.2.6 VIDEO FILTERING
SAA6752HS
The following VBI data formats are supported: Closed Caption (CC525 and CC625) and Wide Screen Signalling (WSS525 and WSS625). For CC525, CC625 and WSS625 the sliced data from a video input processor (e.g. SAA7114) are extracted from the digital video input signal and can be read via the I2C-bus. For WSS525 an internal data slicer is available which slices the oversampled raw data, which are delivered by the video input processor. The extracted WSS525 signal can be read via the I2C-bus. SAA6752HS/V103 allows the automatic insertion of extracted Closed Caption data into the user data area of a video stream (for details see Section 7.3.8). 7.3 7.3.1 Video compression GENERAL
7.2.6.1
Adaptive mean filter
The SAA6752HS uses an adaptive mean filter. There are three different filter modes that can be selected: median, averaging or no filter. The median algorithm provides better noise performance and is well suited to suppress single noise spikes without degrading the signal edges. The averaging algorithm is a standard low-pass filter so has greater impact on signal edges. The default threshold and gain coefficients of this filter can be overwritten via the I2C-bus to allow user optimization for different applications.
7.2.6.2
Horizontal pre-filter/decimation filter
There is a horizontal filter for Y and C and this can operate as a pre-filter or decimation filter. It is a symmetrical FIR filter with up to 8 coefficients programmable via the I2C-bus.
7.2.6.3
Vertical chrominance filtering
For 4 : 2 : 2 to 4 : 2 : 0 conversion, vertical filtering and subsampling of the chrominance is performed. The sequence of coefficients is mirrored in top and bottom field. This generates the right phases of the chrominance samples between the luminance samples (a non co-sited sampling scheme). 7.2.7 VBI DATA EXTRACTION
Compression of video data is performed by the video compressor block; see Fig.4. The input to this block is the uncompressed video information pre-processed by the video front-end and stored in external SDRAM memory. The output is a compressed video stream, compliant to MPEG-2 Video Elementary Stream (VES) up to slice level. Controlling information (for example, quantizer step size) as well as the bit stream for higher layers of the VES is generated by the embedded MIPS(R) processor of the SAA6752HS. The video compressor contains several subblocks. The MacroBlock Processor (MBP) performs generation of video ES on macroblock level. Controlling parameters for this task and MB headers as well as slice headers are generated by the core control subblock. Bitstream formatting and concatenation of MBP bitstream and header information is done by the subblocks pre-packer and packer.
The SAA6752HS supports the extraction of WSS and CC data using two independent VBI data extractor modules. The data is available via the I2C-bus.
2002 Dec 09
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.3.2 VIDEO ENCODER CONFIGURATION OPTIONS Table 3 GOP
SAA6752HS
The following configuration options can be selected from the host: * VIDEO COMPRESSION SETTINGS. I, IP and IPB encoding with various GOP structures can be selected. * ENCODER BIT RATE. The bit rate for variable bit rate or constant bit rate modes can be programmed using bit rate and quantization control parameters. These parameters can be adjusted whilst encoding, not just set at initialization. * ENCODER PERFORMANCE TUNING. The ability for the user to tune encoding performance is provided by allowing control of adaptive quantization depth. Also the SAA6752HS allows download of new quantizer matrix contents. 7.3.3 VIDEO ENCODER STATUS INFORMATION
GOP LENGTH (N) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Notes 1. Undefined.
REFERENCE FRAME DISTANCE (M) 0 I
(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)
1
(1) (1)
2
(1) (1) (1)
3
IP IPP IPPP IPPPP IPP...PP
IBP(2) BIBP(3) IBPBP(2) IBP...BP(2)
IBBP(2)
(1)
IPP...PP BIBPBP(3) IPP...PP BIBP...BP(3) IPP...PP IBP...BP(2) IPP...PP BIBP...BP(3) IPP...PP IBP...BP(2) IPP...PP IBP...BP(2) IPP...PP BIBP...BP(3) IPP...PP IBP...BP(2) IPP...PP BIBP...BP(3) IPP...PP IBP...BP(2) IPP...PP IBP...BP(2)
BBIBBP(3) IBBPBBP(2)
(1)
BBI...BBP(3) IBBP...BBP(2)
(1)
The following status information is available to the host: * CURRENT ENCODER BIT RATE. The actual encoded bit rate, as number of bytes per GOP, is available allowing the use of constrained variable bit rate algorithms to fine tune the encoding efficiency. 7.3.4 GOP STRUCTURE
IPP...PP BIBP...BP(3) BBI...BBP(3) IBBP...BBP(2)
(1)
BBI...BBP(3) IBBP...BBP(3)
(1)
IPP...PP BIBP...BP(3) BBI...BBP(3) IBBP...BBP(2)
The programmable GOP structure features a reference frame distance (M) up to 3, and a GOP length (N) of up to 19. Supported structures are real closed GOP(M,N) and backward predicted closed GOP(M,N). For the use of B-frames in D1 and 2/3D1 mode a 64 Mbit SDRAM is needed. In D1 mode, B-frames will be unidirectional. Backward predicted closed GOPs may have the first one (M = 2) or two (M = 3) B-frames referenced inside the GOP dependent on the I2C-bus register settings. This is intended for editable applications as GOPs are independent of each other. Non-editable GOPs allow the first one (M = 1) or two (M = 2) B-frames to be referenced to the P-frame in the previous GOP. This is a non-editable format but has optimum encoding efficiency. This structure is sometimes called an open GOP. The first one (M = 1) or two (M = 2) B-frames in the first GOP of a sequence are always forced backwards predicted.
2. This GOP structure is defined as a Real Closed GOP (RCG). 3. This GOP structure is defined as a Backward Predicted Closed GOP (BPCG) or Non-Editable GOP (NEG), selectable via the I2C-bus.
2002 Dec 09
19
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.3.5 BIT RATE CONTROL 7.3.7
SAA6752HS
QUANTIZER MATRIX TABLE DOWNLOAD
The SAA6752HS supports two modes of video bit rate control: variable bit rate and constant bit rate. The Variable Bit Rate (VBR) mode is intended for burst data transfer applications, where the bit rate is allowed to vary but the image quality should be constant. In this mode, a combination of three parameters can be set: Rvbr, Qmin_VBR and Qmax_VBR. While aiming at the target bit rate Rvbr, only quantizer scale values within the range between Qmin_VBR and Qmax_VBR are applied. Broadening this range leads to greater variations in picture quality but better adherence to Rmax. Constriction of this range forces a better constancy in picture quality at the expense of meeting the target bit rate. Note that optimal control results require reasonable combinations of Rmax, Qmin_VBR and Qmax_VBR. Furthermore, the maximum bit rate Rmax can be set. If Rmax is reached in VBR mode, the CBR algorithm takes over the control by increasing the quantizer scale values temporarily (over Qmax_VBR) to guarantee that Rmax is never exceeded. Hence, the closer Rmax and Rvbr are chosen, the more the control in VBR mode turns to CBR mode behaviour. The Constant Bit Rate (CBR) mode is intended for applications, where a fixed channel rate is provided (e.g. transmission systems). A tight control of the quantizer scale is applied to make optimal use of the given bandwidth. The parameter Rmax specifies the required constant bit rate. Independent of the bit rate mode (CBR or VBR), a B-frame weighting factor (the weighting factor is applied to the quantization scale) can be applied to further reduce the bit rate of B-frames. In IP-only GOP structures, every second P-frame is weighted by this factor generating `virtual B-frames' to simulate a bit rate distribution similar to IPB sequences. This feature can further improve the perceptual rate-distortion ratio by taking advantage of the inertia of the human visual system. 7.3.6 ADAPTIVE QUANTIZATION
The MPEG standard default quantizer matrices can be overwritten to allow picture encoding optimization. 7.3.8 USER DATA INSERTION
User data insertion of up to 64 bytes is supported on GOP and picture level. The ROM code versions V101 and V102 of SAA6752HS allow only in Idle mode the download of user data for the user data 1 area (GOP level) and/or user data 2 area (picture header level). Therefore no dynamic user data insertion is possible during Encode mode. The ROM code version V103 has got an enhanced user data insertion; the different modes can be selected via I2C-bus.
7.3.8.1
External user data insertion (permanently repeated) (only for SAA6752HS/V103)
This mode is similar to the user data insertion in ROM code versions V101 and V102: user data is downloaded via the I2C-bus to subaddresses 73H/76H and the number of inserted user data bytes is set via subaddresses 74H/75H. In Encode mode the downloaded user data will be inserted permanently into the user data area of the video stream. With ROM code version V103 it is possible to download a new set of user data during Encode mode. The new data will be repeatedly inserted as soon as the download is finished. It is possible to stop the user data insertion with a special command.
7.3.8.2
External user data insertion (each downloaded byte inserted only once) (only for SAA6752HS/V103
Adaptive quantization is an algorithm that uses internal generated statistics to fine tune the quantizer scale used for encoding a specific macroblock. For example, the controller adapts the quantization scale with respect to the local complexity distribution within a frame, resulting in a perceptually smoother picture quality. The amount of fine tuning can be adjusted by control of the adaptive quantization depth.
In this mode each downloaded user data byte is inserted only once into the user data area. If no new user data is downloaded between two GOP or pictures then no user data will be inserted. This mode can be used to transmit more than 64 bytes of user data from the encoder to the decoder, e.g. 1000 bytes distributed on 15 packets of 64 bytes and one packet of 40 bytes. The host has to control the insertion and repetition of user data. A host interrupt 'mode transition completed' is signalled, if not masked and the bit 9 of the exception status word is set when the user data have been read by the video encoder. Then new user data can be downloaded via I2C-bus.
2002 Dec 09
20
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.3.8.3 Internal Closed Caption user data insertion compliant to ATSC/NTSC standard (only for SAA6752HS/V103)
SAA6752HS
Closed Caption data, which is delivered from the video input processor (e.g. SAA7114) and captured in the video front-end will be inserted into the user data 1 area (GOP header level) of the video stream. Preconditions are appropriate settings of the video input processor and the VBI data extractor in the video front-end. The Closed Caption user data will be written for both fields. If no valid Closed Caption data for field 2 is available these data will be marked as invalid in the stream. If extended data services (XDS data, line 21 field 2) are inserted, the insertion will be transparent. No modification of the CGMS-A copy information will be done. The Closed Caption data will be inserted for each field of the GOP in display order. At SIF mode only field 1 Closed Captions can be inserted from the video input signal and dummy values (80H 80H) will be inserted for field 2. The user data is delayed by one GOP period. The first GOP in the stream carries dummy data marked as invalid. No additional user data on GOP header level can be inserted if internal Closed Caption user data insertion compliant to the DVD standard is active. The amount of user data depends on the GOP size: 5 bytes header and 3 bytes/field are required. With the maximum GOP size of 19 this results in 5 + 19 x 2 x 3 = 119 bytes, which is more than the available array of 64 bytes for GOP user data. Therefore the 64 byte array for picture user data is also used for GOP user data, if GOP sizes larger than 9 are selected. Then all 128 bytes, which are available for user data insertion on GOP and picture header level will be used for the insertion of CC data on GOP level. In this case no additional user data insertion on picture header level is possible. 7.3.9 MOTION ADAPTIVE NOISE REDUCTION
Automatic insertion of Closed Caption data into the user data 2 area on picture header level compliant to the ATSC and EIA-708 standard can be selected via the I2C-bus. Closed Caption data, which is delivered from the video input processor (e.g. SAA7114) and captured in the video front-end will be inserted into the user data 2 area (picture header level) of the video stream. Preconditions are appropriate settings of the video input processor and the VBI data extractor in the video front-end. The Closed Caption user data will be written for both fields. If no valid Closed Caption data for field 2 is available these data will be marked as invalid in the stream. At SIF mode only field 1 Closed Captions can be inserted from the video input signal and dummy values (80H 80H) will be inserted for field 2. If extended data services (XDS data, line 21 field 2) are inserted, the insertion will be transparent. No modification of the CGMS-A copy information will be done. In accordance to EIA-708 the Closed Caption data will appear in the stream in transport order. If B-frames are present the user data is re-ordered in the same way as the video frames. Advanced TV Closed Captioning (ATVCC) channel packet data (cc_type 10 or 11) is not supported, because the input signal of the encoder is an analog video signal, which can carry only NTSC Closed Captions, but not ATV Closed Captions. No additional user data on picture header level can be inserted if internal Closed Caption user data insertion compliant to the ATSC/NTSC standard is active.
7.3.8.4
Internal Closed Caption user data insertion compliant to DVD standard (only for SAA6752HS/V103)
The gain and adaptivity can be controlled to optimize encoding efficiency in case of noisy input sequences, i.e. off-air reception.
Automatic insertion of Closed Caption data into the user data area on GOP header level compliant to the DVD standard can be selected via I2C-bus.
2002 Dec 09
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.3.10 COMPRESSION BLOCK PARTITIONING
SAA6752HS
* Pre-packer (part of packing unit). Since the MBP output words are not necessarily fully used (i.e. some output words may contain unused bits) the pre-packer packs the output of the MBP in such a way that all words contain valid bits. This reduces the amount of memory required for storing the MB data. * Packer (part of packing unit). Merges header and MB headers.
The video compression block, shown in Fig.4, contains the following sub-modules: * MacroBlock Processor (MBP). Reads uncompressed video data from SDRAM and generates the compressed bitstream on MB level (without MB headers). Addresses for frame buffer (previous frame) access are generated by the MBP. * Core control. Performs MB and slice header generation, base address generation for the current MB (uncompressed), motion vector candidate generation, and computation of encoding statistics required by the CPU for bit rate controlling.
handbook, full pagewidth
to/from SDRAM-IF
to SDRAM-IF
VIDEO COMPRESSION BLOCK PACKING UNIT MBP/CPM PREPACKER MEMORY PACKER
from video front-end
CORE CONTROL
GENERIC INTERFACE
MHC131
to/from PCI-bus
Fig.4 Video compressor block diagram.
2002 Dec 09
22
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.4 7.4.1 Digital audio input GENERAL 7.4.3 INPUT FORMATS
SAA6752HS
The audio input interface (I2S) accepts serial digital audio data and supports master and slave mode. The interface is able to handle 16 to 20 bits audio data with left and right channel. Audio data with more than 20-bit word width is accepted as input, but the additional bits are ignored. 7.4.2 AUDIO PORT CONFIGURATION OPTIONS
The digital audio input interface can select between two digital audio input ports via I2C-bus control and is able to input the following audio formats: * I2S, see Fig.5 * EIAJ, see Fig.6 * EIAJ alternative format. The alternative formats are defined as having the word select shifted by one clock cycle with respect to the data. EIAJ and EIAJ alternative format are supported for 16, 18 and 20-bit resolution. I2S and I2S alternative format are supported for 16, 18, 20 and 24-bit resolution. Input data is truncated to 20 bits internally if 24-bit resolution is applied. Each of the formats can be applied in master or slave mode. When in master mode, the external audio analog-to-digital convertor must be clocked using the audio clock generated by the SAA6752HS. This can be set to 256 x 48 kHz or 384 x 48 kHz (locked to the video frame frequency). In slave mode an internal sample rate converter converts the input sample frequency to a video frame locked 48 kHz sample frequency.
The following configuration options can be selected from the host: * AUDIO INPUT PORT SELECTION. Two digital audio input ports are selectable. * AUDIO INPUT FORMAT. Various I2S and EIAJ formats can be selected. * AUDIO INPUT MODES. Master or slave mode can be selected. * AUDIO CLOCK OUTPUT. An audio clock output (256 x 48 kHz or 384 x 48 kHz) can be used for external analog-to-digital converter clocking. * AUDIO OUTPUT. The second audio interface port can be configured as output in special applications e.g. concurrent encoding of audio and video without internal multiplexing of the two streams.
2002 Dec 09
23
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SAA6752HS
handbook, full pagewidth I 2S
1 stereo word
SWS
left data
right data
SCLK
SDATA
MSB
LSB
MSB
LSB
MSB
MHC132
Fig.5 I2S mode format protocol.
handbook, full pagewidth
EIAJ
1 stereo word
SWS
left data
right data
SCLK
SDATA
LSB
MSB
LSB
MSB
LSB
MHC133
Fig.6 EIAJ mode format protocol.
2002 Dec 09
24
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.4.4 AUDIO INPUT PROCESSING
SAA6752HS
In order to be able to cope with analog and digital sources, the I2S input ports can be configured as master (analog) or slave (digital). For the slave mode however, a sample rate converter will be involved, except for DVD-compliant audio bypass. Table 4 reflects the different configuration possibilities. Table 4 Audio input processing modes AUDIO CONTENT FORMAT LPCM at 16, 18, 20 or 24 bits(5)(6) LPCM at 16, 18, 20 or 24 bits(5) LPCM at 16, 18, 20 or 24 bits(5) 16 bits(9) INPUT SAMPLE FREQUENCY (kHz) MASTER(2) 48 SLAVE(3)(4) 32 kHz 0.1% 44.1 kHz 0.1% 48 kHz 0.1% 32 kHz 0.1% 44.1 kHz 0.1% 48 kHz 0.1% 32 kHz 0.1% 44.1 kHz 0.1% 48 kHz 0.1% 48 kHz(10) NO. OF ENCODED BITS 20 ENCODED BIT RATE (kbits/s) 256, 384
PROCESSING
MODE(1)
MPEG-1 L2 encoding
DDC encoding(7)
48
20
256, 384
LPCM bypass (uncompressed audio format)(8) DVD-compliant audio bypass Notes
48
16
-
-
16
-
1. Processing modes can be changed when SAA6752HS is in Idle mode. 2. In master mode, the external audio source must use the SAA6752HS audio clock as a clock source. 3. A sample rate conversion process will convert incoming data to a nominal 48 kHz audio frequency that is locked to V-sync of the video input signal (if present). The sample rate converter is not enabled for DVD-compliant bypass mode. 4. The sample rate conversion input frequency range has been selected to be compatible with class 2 SPDIF receivers. 5. 24-bit input option only applies to I2S input formats, in this event it will be truncated to 20 bits internally in the SAA6752HS before processing. EIAJ formats are limited to 20 bits maximum. 6. The MPEG encoder gain is set to -3 dB. 7. Only for SAA6752HS/V101 and SAA6752HS/V103. 8. In systems that use 16 Mbit SDRAM due to system architecture constraints, LPCM bypass must be restricted to be used with I and IP video encoding only. There is no constraint if 64 Mbit SDRAM is used. 9. The IEC 60958 format defines 20 bits for an audio sample, plus 4 auxiliary bits, which can be used to extend the word length. IEC 61937 uses only 16 data bits of each IEC 60958 sub-frame. It depends on the settings of an external SPDIF to I2S converter if 16, 18, 20 or 24 bits are transferred to the SAA6752HS. 10. For DVD-compliant bypass mode the audio clock must be locked to the video clock externally.
2002 Dec 09
25
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.5 7.5.1 Audio compression GENERAL
SAA6752HS
* DVD-BYPASS HEADER INFORMATION. Header information is available to allow the host to determine the content of the bypassed audio data stream. This includes information from the Preamble Pc, Preamble Pd and audio frame headers. 7.5.4 MPEG-1 LAYER 2 ENCODING
The digital audio signal from the I2S input port is compressed according to MPEG-1 layer 2 and DDC (AC-3) encoding (only for SAA6752HS/V101 and SAA6752HS/V103). The constant bit rate is programmable via the I2C-bus. An audio stream with 16 to 20 bits and a sampling frequency of 48 kHz can be processed. A higher accuracy of more than 20 bits is ignored. A bypass mode can be selected for LPCM for 16-bit data resolution and compressed audio signals (MPEG-1 layer 2, MPEG-2, DD and DTS) according to IEC 61397 or LPCM. The format of such compressed inputs is identified and made accessible via the I2C-bus. 7.5.2 AUDIO ENCODER CONFIGURATION OPTIONS
MPEG-1 layer 2 encoding can be selected. The available I2C-bus settings are: * No pre-emphasis (default setting) * 50/15 s (compliant to ISO 11172-3) * CCITT J.17 (compliant to ISO 11172-3). 7.5.5 DDC ENCODING (ONLY FOR SAA6752HS/V101 SAA6752HS/V103)
AND
The following configuration options can be selected from the host: * AUDIO PROCESSING MODES. MPEG-1 L2 or DDC (AC-3) encoding (only for SAA6752HS/V101 and SAA6752HS/V103) modes can be selected. Two bypass modes are also available: LPCM bypass and DVD-compliant bitstream bypass. * AUDIO MUTE. It is possible to mute the audio data prior to encoding. 7.5.3 AUDIO ENCODER STATUS INFORMATION
Dolby(R) Digital Consumer (DDC) encoding mode can be selected. The encoder performance is suitable for consumer electronic recordable DVD systems. 7.5.6 LPCM BYPASS
16-bit LPCM audio streams can be bypassed by the audio encoder module. 7.5.7 DVD-COMPLIANT AUDIO BYPASS
The following configuration options can be selected from the host: Table 5 DVD-compliant audio bypass MODE MPEG-1/2 layer 2 without extension MPEG-2 layer 2 with extension Dolby(R) digital DTS-1 7.6 7.6.1 SDRAM interface GENERAL BIT RATE 64 to 384 kbit/s up to 912 kbit/s 64 to 448 kbit/s 192 to 1536 kbit/s
DVD-compliant bypass and pause burst handling is selectable in accordance to IEC 61937. Preamble Pc, Preamble Pd and part of the elementary stream header are captured and made available via the I2C-bus. If any non DVD-compliant formats are detected then these are flagged via host interrupt.
SAMPLE FREQUENCY 48 kHz only 48 kHz only 48 kHz only 48 kHz only
CHANNEL CONFIGURATION mono, stereo or multi-channel up to 7.1 mono, stereo or multi-channel up to 7.1 1/0, 2/0, 3/0, 2/1, 3/1, 2/2 and 3/2 stereo or multi-channel up to 5.1
The external SDRAM is used as memory for storing video and audio information during the compression process. It is also used as a buffer for the output stream. The interfacing to and from the functional blocks is done via a number of internal FIFO memories. 2002 Dec 09 26
The SAA6752HS will support 16 Mbit@16 bit (512k x 16 x 2) and 64 Mbit@16 bit (1024k x 16 x 4) SDRAM devices. The minimum recommended speed of the SDRAM is 125 MHz. Recommended SDRAMs include the Samsung K4S641632D-TC/L80 and K4S161622D-TC/L80 devices.
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.7 7.7.1 Multiplexer GENERAL 7.7.6 PROGRAM STREAM OUTPUT
SAA6752HS
The system stream multiplexer combines compressed audio and video streams into a single MPEG system stream. Presentation data is synchronized by the use of time stamps as specified in the MPEG systems standards. The multiplexer ensures an MPEG-compliant multiplexing with respect to buffer maintenance, synchronization and data alignment. It takes care of the system specific requirements for D-VHS, DVD, DVB and ATSC. 7.7.2 MULTIPLEXER CONFIGURATION OPTIONS
Program stream output, intended for storage recording applications, can be selected. Time slot reservation for navigation packets is available. Metabytes can be appended after each pack, see Section 7.7.10. 7.7.7 PACK STREAM OUTPUT
The following configuration options can be selected from the host: * STREAM FORMAT. Selection of audio or video elementary stream, packetized elementary stream, program stream or transport stream options and general system parameters including maximum system bit rate, number of flushing bytes and PES header IDs. * TRANSPORT STREAM SYSTEM MODES. In TS mode, it is possible to set packet IDs and download system information tables. 7.7.3 MULTIPLEXER STATUS INFORMATION
A special mode called pack stream can be selected. This is a program stream but without the MPEG buffer model implemented. This minimizes the throughput time of video and audio data through the SAA6752HS and is intended for applications where low latency is important. In this mode no program stream header is inserted. 7.7.8 TRANSPORT STREAM OUTPUT
Transport stream output can be selected. The video, audio and PCR (clock) Packet Identifiers (PIDs) can be programmed. System information tables can be transferred to the SAA6752HS via the I2C-bus. If transport stream output is combined with DIO master mode as output mode then packets are sent in a controlled way, so that a set-top box can be connected.
7.7.8.1
Transport stream with variable bit rate (only for SAA6752HS/V103)
The following status information can be selected from the host: * METABYTES INFORMATION. If selected and in program stream or pack stream, it is possible to insert video and audio status information into the stream output as special metabyte data packets for later system processing. * NUMBER OF BYTES PER GOP. It is possible to read the current system bit rate of the output stream. 7.7.4 ELEMENTARY STREAM OUTPUT
Optionally a transport stream without null packets, i.e. with variable bit rate can be generated. Via subaddress C3H it is possible to select constant or variable TS bit rate. At constant TS bit rate mode null packets are delivered at the multiplexer output to achieve the constant TS bit rate, even if the video bit rate is variable. At variable TS bit rate mode no Null Packets are inserted at the multiplexer output. This mode can be used in combination with variable video bit rate. 7.7.9 INSERTION OF LEADING NULL BYTES
Video and audio elementary stream outputs can be selected. 7.7.5 PACKETIZED ELEMENTARY STREAM OUTPUT
Packetized Elementary Stream (PES) outputs can be selected. There are two options: PES (DVD) and PES (TS). Variable bit rate is only available in PES (DVD) mode and constant bit rate only available in PES (TS) mode. The video and audio PES IDs can be programmed via the I2C-bus. Original copy or copyright flags can also be set.
For some applications it is helpful to deliver leading flushing bytes before the stream content starts. Null bytes (00H) will be inserted at the beginning of a stream, if programmed by subaddress F6H. By default no null bytes will be delivered.
2002 Dec 09
27
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.7.10 METABYTES DATA
SAA6752HS
In program stream and pack stream modes, the SAA6752HS can append additional metabyte data packets to the stream, providing information on sector information for downstream application processing. The video and audio metabytes format is defined in Tables 6 and 7. The sector and metabytes form a block format, where each sector of 2048 bytes is followed by 16 metabytes containing data on the previous sector. Table 6 BYTE (HEX) 00 01 flags Video metabytes data NAME identification LSB/ MSB BIT 0 to 7 0 1 2 55H; video `GOP start flag'; indicates that a GOP start code is present in the sector `GOP start header'; indicates that a group of GOPs starts in the sector `sequence end flag'; indicates that a sequence end code is present in the sector undefined amount of non-stuffing bytes minus one The value of the STC at the moment that the first byte of the first frame arrived at the input. Only 32 bits are used; note 1. DESCRIPTION
3 and 4 reserved 5 to 7 02 03 04 05 06 07 08 09 picture start count picture types MSB time stamp data length LSB MSB LSB 0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 the amount of picture starts in the sector 0 and 1 1st picture type: 00: I picture 01: P picture 10: B picture 11: invalid type 2 reserved 4 and 5 2nd picture type: 00: I picture 01: P picture 10: B picture 11: invalid type 6 0A 0B 0C 0D 0E 0F Note 1. This is the same value as used to generate the PTS and DTS values. 2002 Dec 09 28 GOP header position second picture position first picture position LSB MSB LSB MSB LSB MSB 0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 reserved position (in bytes) of the first picture (or GOP or sequence) start code in the sector position (in bytes) of the first picture (or GOP or sequence) start code in the sector position (in bytes) of the GOP start code in the sector, if present, else 0000
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
Table 7 BYTE (HEX) 00 01 flags Audio metabytes data NAME identification LSB/ MSB BIT 0 to 7 0 1 AAH; audio reserved DESCRIPTION
SAA6752HS
`terminated audio flag'; this flag is only set at the end of a recording session and indicates that this sector is not completely filled with audio data `synchronization flag'; indicates that the audio data in the sector is related in time to the beginning of a Video Object Unit (VOBU) reserved reserved audio pack type: 000: MPEG-1 layer 2 or MPEG-2 without extension 010: MPEG-2 with extension 011: DDCE 100: DTS-1 (512 samples/frame) 101: reserved 110: reserved 111: LPCM 16-bit stereo 48 kHz amount of non-stuffing bytes minus one The value of the STC at the moment that the first byte of the first frame arrived at the input. Only 32 bits are used; note 1.
2 3 4 5 to 7
02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Note
data length time stamp
LSB MSB LSB
0 to 7 0 to 7 0 to 7 0 to 7 0 to 7
MSB reserved frame start count first frame position last frame position reserved reserved LSB MSB LSB MSB
0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 0 to 7 00 00 position (in bytes) of the last frame in the sector 00 the amount of frame starts in the sector position (in bytes) of the first frame in the sector
1. This is the same value as used to generate the PTS value.
2002 Dec 09
29
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.8 7.8.1 MPEG stream output port GENERAL 7.8.4 Table 8 PORT PDIDS PDIOCLK PROTOCOL DESCRIPTION Output port definitions I/O I
SAA6752HS
The MPEG stream output port connects the SAA6752HS multiplexer output to the outside world. The parallel interface performs a parallel output transition of audio and video data to an externally connected device and supports 3-bus protocol modes. 7.8.2 OUTPUT PORT CONFIGURATION OPTIONS
DESCRIPTION Request from external system if interface is in DEBI slave mode.
I/O Output clock to the external system if interface is set to DIO master mode. Input clock to the SAA6752HS if interface is set to DIO slave mode. O O O O output data (8-bit parallel) Indicates a first byte of a data packet (for transport streams in DIO mode). Indicates when an audio packet is output (for transport stream). Indicates whether currently sent data is valid.
The following configuration options can be selected from the host: * OUTPUT PROTOCOL. Three output protocols can be selected: DIO slave mode, DIO master mode and DEBI slave mode and associated signalling pin polarities. * OUTPUT DISABLE. Output can be set to high-impedance if the SAA6752HS is not used in application. 7.8.3 DATA OUTPUT FORMAT
PDO[7:0] PDOSYNC PDOAV PDOVAL
7.8.4.1
DIO master mode
The data to be transmitted have a width of 8 bits in all modes. The data output port supports DIO and DEBI bus protocols. The bus protocol mode is set via an I2C-bus controlled register. The DEBI protocol provides only a transmission of 8-bit data block transfer without address decoding.
The PDIOCLK clock for the DIO interface is derived from the system clock by a division of the 27 MHz clock by 3 or by 4, generating a data output clocked at 9 or 6.75 MHz. A PDOVAL signal indicates whether current data at the output is valid. If the output buffer is empty the PDOVAL signal will stay LOW. The number of valid pulses indicate the real number of data transmissions. The signal PDOSYNC in conjunction with PDOVAL indicates the first byte of a transport stream packet.
handbook, full pagewidth
SAA6752HS
OUTPUT INTERFACE PDIOCLK PDOSYNC PDOAV PDO [7:0] PDOVAL PDIDS n.c.
DATA RECEIVER CLOCK DSYNC AUDIO/VIDEO QUALIFIER DATA VALID
MHC134
Fig.7 DIO master mode protocol.
2002 Dec 09
30
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SAA6752HS
handbook, full pagewidth PDIOCLK
PDO [7:0]
00
01
BA
PDOVAL
MHC135
Fig.8 Data transfer in DIO master mode.
handbook, PDIOCLK full pagewidth
PDOVAL
PDO [7:0] 188 bytes PDOSYNC
MHC136
Fig.9 DIO master mode, transport stream packet.
2002 Dec 09
31
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.8.4.2 DIO slave mode
SAA6752HS
The SAA6752HS can be enabled in a DIO slave mode where the data receiver acts as master. PDO, PDOSYNC and PDOAV are clocked out by the internal clock; earliest two internal clock cycles e.g. 36 to 58 ns after the falling edge of the external clock. The external clock PDIOCLK should not exceed a maximum of 9 MHz. The PDOVAL signal still indicates if data is available in the output buffer. To operate in this mode, the PDIDS request input must be set to logic 1.
handbook, full pagewidth
SAA6752HS
OUTPUT INTERFACE PDIOCLK PDOSYNC PDOAV PDO [7:0] PDOVAL PDIDS '1'
DATA RECEIVER CLOCK DSYNC AUDIO/VIDEO QUALIFIER DATA VALID
MHC137
Fig.10 DIO slave mode protocol.
handbook, full pagewidth PDIOCLK
PDO [7:0]
10
00
01
BA
PDOVAL
MHC138
Fig.11 Data transfer in DIO slave mode.
2002 Dec 09
32
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.8.4.3 DEBI slave mode
SAA6752HS
Note that to operate correctly to the DEBI transfer protocol the VALID output signal should be programmed negative by I2C-bus command and a 3.3 k resistor to VDDP is recommended.
The SAA6752HS supports DEBI slave mode with a block transfer of 8-bit data. This can be used for interfacing with a PCI bridge (for example, an SAA7146A chip set). There is no addressing phase necessary. The transfer starts with recognition of a PDIDS pulse. The requested data, PDO[7:0], is transferred when the PDOVAL signal goes active, indicating that data is available in the output buffer. In the event of interfacing to an SAA7146A chip set, the PDOVAL pin is connected to the DTACK_RDY pin and serves as a handshake. The LDS_RDN and UDS_WRN signals should be used to generate the PDIDS signal.
handbook, full pagewidth
SAA6752HS
OUTPUT INTERFACE PDIOCLK PDOSYNC PDOAV PDO [7:0] PDOVAL PDIDS n.c. n.c. n.c.
DATA RECEIVER (SAA7146A)
AD16IN DTACK_RDY LDS_RDN UDS_WRN
MHC139
Fig.12 DEBI slave mode protocol.
handbook, full pagewidth
PDIDS
PDO [7:0]
XX
01
XX
02
PDOVAL
MHC140
Fig.13 Data transfer in DEBI slave mode.
2002 Dec 09
33
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.9 7.9.1 Clock generation GENERAL
SAA6752HS
* CLOCK OUTPUT. It is possible to enable a system clock output so that the 27 MHz clock can be used elsewhere by the user. 7.9.3 CLOCK MODES
The SAA6752HS is designed to operate with a single fundamental 27 MHz crystal or an external 27 MHz clock. From these clock sources an internal PLL produces the 27 MHz, 54 MHz and 108 MHz frequencies needed for operation. It is possible to use a third overtone crystal in combination with a 9 MHz external trap. In this event Clock mode 2 and tuning by the I2C-bus commands are not usable. 7.9.2 CLOCK CONFIGURATION OPTIONS
The SAA6752HS internal PLL can be configured in three different clock modes: Clock modes 1, 2 and 3. A definition of the clock modes is shown in Table 9. The clock modes are intended for different applications: * Clock mode 1. System clock reference locked to input video frame frequency. Intended for applications where the output stream is recorded directly onto a medium (i.e. DVD video recorder). * Clock mode 2. Crystal locked to input video frame frequency. Intended for applications that require both recording and direct playback. However it is limited by the required accuracy of the input video frame frequency * Clock mode 3. Crystal free-running. Intended for applications where the output stream is played real time directly by a decoder. To meet the requirements for each clock mode the conditions specified in Table 10 must be met.
The following configuration options can be selected from the host: * CLOCK MODE. Dependent on the type of application (i.e. video frame locked, reference clock locked etc.), three different clock modes are available * CLOCK SOURCE. The clock can be generated from an internal crystal controlled clock or an external source. If from a crystal then a fine tune adjustment is available
Table 9
Clock modes SYSTEM FREQUENCY crystal frequency 27 MHz video frame frequency accuracy crystal frequency SYSTEM CLOCK REFERENCE FREQUENCY 27 MHz video frame frequency accuracy 27 MHz video frame frequency accuracy crystal frequency
CLOCK OUTPUT STREAM MODE TIME-STAMP COMPLIANCE 1 2 3 Note DVD-compliant(1) DVD and MPEG-compliant MPEG-compliant
1. The stream contents are MPEG-compliant but the time stamps are not synchronized with real time (i.e. dependent on the accuracy of the video input frame frequency). Playback of such a stream is MPEG-compliant due to the re-generation of time synchronization. Table 10 Clock modes requirements CLOCK MODE 1 2 3 Note 1. The nominal video frame frequency is dependent on the video mode set: 525 or 625 lines. CRYSTAL FREQUENCY 27 MHz 0.1% 27 x (1 200 x MHz (to allow fine tuning via PLL) 27 x (1 30 x 10-6) MHz 10-6) EXTERNAL CLOCK FREQUENCY 27 MHz 0.1% not applicable 27 x (1 30 x 10-6) MHz INPUT VIDEO FRAME FREQUENCY(1) nominal - 8% to nominal + 2% nominal x (1 200 x 10-6) not applicable
2002 Dec 09
34
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
7.9.4 CLOCK MODE 2 AUTO-SWITCH 7.11 7.11.1 I2C-bus interface GENERAL
SAA6752HS
An auto-switch mode is available if Clock mode 2 is selected. In this event the PLL will switch to Clock mode 1 or 3 if the conditions for Clock mode 2 are no longer met (i.e. video frame frequency outside the range 1 200 x 10-6). The auto-switch preference is set by an I2C-bus command during the SAA6752HS initialization. If auto-switch occurs then a host interrupt can be flagged. 7.9.5 CRYSTAL TUNING
The I2C-bus interface within the SAA6752HS is a slave transceiver. It is used for all control settings. The read mode may be used to read back error or status codes. The I2C-bus interface is compliant to the I2C-bus standard at 100 kHz and 400 kHz clock frequency and suitable for bus line voltage levels of 3.3 V. If an I2C-bus with higher voltage is used by an application, it is possible to add a small interface between 3.3 V and a higher voltage level. Only two MOSFET transistors (e.g. BSN10, BSN20 or BSS83) are needed. A description of this circuit is available at http://www.semiconductors.philips.com/i2c/facts/ Information about the I2C-bus can be found in the brochure "The I2C-bus and how to use it" (order number 9398 393 40011). 7.11.2 SLAVE ADDRESSES
It is possible to tune the crystal frequency by up to 1 200 x 10-6 via the I2C-bus. If necessary this can be used to achieve the MPEG-2 accuracy of 1 20 x 10-6 with standard crystals. 7.9.6 EXTERNAL CLOCK SOURCE
It is possible to use an external system clock. For start-up before switching to the external clock input a crystal has to be connected or the external frequency has to be applied to pin XTALI. The input voltage for this pin must be limited to 2.5 V. An external clock source cannot be used with Clock mode 2. 7.9.7 AUDIO CLOCK
A switchable sampling frequency for an audio Analog-to-Digital Converter (ADC) is generated by the internal PLL. Two sampling frequencies are selectable: 256 x 48 kHz and 384 x 48 kHz. This clock output can be used as clock signal for an external audio ADC. The system clock reference frequency as described in Table 9, is used as reference for the internal PLL generating the audio clock. 7.10 7.10.1 Power control and reset GENERAL
Two write I2C-bus slave addresses (SAD) are available, 40H and 42H (8-bit), dependent on the state of address select pin I2CADDRSEL. This avoids possible address conflict of addresses with other devices. A HIGH-level at the address selection pin will set the device write address to 42H. Similarly for read operations there are two slave addresses: 41H and 43H. A HIGH-level at the address selection pin will set the device read address to 43H. 7.12 7.12.1 Exception handling GENERAL
An external reset pulse at power-up is needed to start-up the SAA6752HS. This will start the oscillator and initialize hardware and firmware. The SAA6752HS can be set to a power saving sleep mode where all internal clocks are switched off. In this mode restarting can only be done by a hard reset pulse.
The SAA6752HS is capable of flagging certain events to a host via a host interrupt flag pin H_IRF. The host is able to read back a 16-bit status word via the I2C-bus to identify the specific event and take action accordingly. Detectable events include copyright violations, loss of input synchronization, DVD compliance errors etc. 7.12.2 EXCEPTION CONDITIONS
A list of the SAA6752HS exception conditions, as indicated by the status word, is defined in Table 11. The I2C-bus subaddress is 12H (see Table 14).
2002 Dec 09
35
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
Table 11 Interrupt status definition STATUS WORD BIT 0 1 EXCEPTION CONDITION video copyright violation input video signal not detected or lost
SAA6752HS
RESPONSE IF EXCEPTION IS DETECTED SAA6752HS continues encoding; note 1. SAA6752HS continues encoding but outputs audio ES packets only; SAA6752HS will resynchronize if video input is recommenced; notes 2 to 4.
2
SAA6752HS continues but frames may be lost during when a difference between the V-sync period in I2C-bus settings and in the video input signal the event. is detected Clock mode 2 out of range output buffer overflow (due to loss of data read command) video and audio frames out of alignment If enabled, the SAA6752HS PLL will auto-switch to Clock mode 1 or 3 as programmed. Stream output stops or corrupted data will be delivered; reset or forced reconfigure needed to recover. Ratio between number of generated audio frames and number of generated video frames is not nominal; time stamps remain correct; note 5. SAA6752HS continues encoding but will not include audio packets.
3 4
5
6
input audio not DVD-compliant (to IEC 61937) * incorrect Preamble Pc * sampling frequency out of range * bit rate out of range
7 8 9
audio format change detected in DVD bypass mode audio pause burst detected SAA6752HS mode transition complete; desired operation mode has been reached only for SAA6752HS/V103: if external user data insertion in mode `only once' is active: insertion of user data has been finished and the host can send new user data
SAA6752HS continues encoding but will not include audio packets. SAA6752HS continues operation. SAA6752HS continues operation.
10
illegal I2C-bus command * I2C-bus command not recognized * command in invalid mode * command parameter error
SAA6752HS ignores the I2C-bus command.
11
general error
SAA6752HS will go to Idle mode if time-out is enabled or stop operating if time-out is disabled; in case of the later a forced reconfigure is recommended. SAA6752HS continues encoding but outputs video ES packets only; transition to STOP needed to recover. SAA6752HS continues operation.
12
input audio word select signal not detected or audio stream stopped after exception status bit 4, 6, 7 or 8 VBI WSS data has been captured
13
2002 Dec 09
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
STATUS WORD BIT 14 15 EXCEPTION CONDITION VBI CC data has been captured only for SAA6752HS/V101 and SAA6752HS/V102: video frame drop only for SAA6752HS/V103: memory manager resynchronization occurred after discontinuity in the video input signal Notes 1. `No copy' flag is only detected if the correct WSS VBI mode is enabled.
SAA6752HS
RESPONSE IF EXCEPTION IS DETECTED SAA6752HS continues operation. SAA6752HS continues operation, video and audio output restart resynchronized. SAA6752HS continues operation, but a forced reconfigure is recommended.
2. This error flag detects mismatches between the input video format (525 or 625) and SAA6752HS video setting (525 or 625). Video syncs out of range are also detected. 3. A loss of video sync is flagged if 10 consecutive syncs are not detected. 4. For stream types which include video mode transitions to encode or idle/stop will not be finished, if no video is present. A pending mode transition can be stopped by forced reconfigure. 5. In clock mode 1 and 3 this can occur due to discontinuity in the video input signal. In applications, which require an exact ratio between the number of generated audio frames and the number of generated video frames, the host might start a corrective action. In clock mode 3 this exception can be ignored; it will happen after some encoding time, because the audio processing is locked to the system frequency and video processing depends on the video input frequency. 7.12.3 HOST INTERRUPT OPERATION A file containing the detailed Boundary Scan Description Language (BSDL) description of the SAA6752HS is available on request. 8.1 Initialization of boundary scan circuit
A LOW level as signalled by the host interface pin indicates that an exception condition has been detected. The host interrupt flag pin H_IRF is reset to HIGH by reading the interrupt status word via the I2C-bus. 7.12.4 INTERRUPT MASKING
It is possible to mask any combination of exception conditions by setting a 16-bit interrupt mask via the I2C-bus. 8 BOUNDARY SCAN TEST
The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET), when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting pin TRST to LOW. 8.2 Device identification codes
The SAA6752HS has built-in logic and 5 dedicated pins to support boundary scan testing, which allows board testing without special hardware (nails). The SAA6752HS follows the "IEEE Std. 1149.1 - Standard Test Access Port and Boundary Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are: Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 12). Details on the JTAG BST-TEST can be found in the specification "IEEE Std. 1149.1". 2002 Dec 09 37
A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service. When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDI and TDO of the IC.
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SAA6752HS
The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO); see Fig.14. Table 12 BST instructions supported by the SAA6752HS INST BYPASS EXTEST SAMPLE DESCRIPTION This mandatory instruction provides a minimum length serial path (1-bit) between TDI and TDO, when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing, when not all ICs have BST. It addresses the bypass register, while the boundary scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number.
CLAMP IDCODE
handbook, full pagewidth
MSB 31 TDI 28 27 0010 1011 0110 0110 16-bit part number E M S 12 11 1
LSB 0 1 TDO
XXXX 4-bit version code
0000 0010 101 11-bit manufacturer identification
MHC141
Fig.14 32 bits of identification code.
2002 Dec 09
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This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 9 I2C-BUS CONTROL AND STATUS REGISTERS 2002 Dec 09 2002 Dec 09 39 39 Philips Semiconductors
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
Tables 13 to 26 list the I2C-bus instructions intended for functional control and status. Column M identifies the SAA6752HS modes that are valid for each I2C-bus instruction. The key is: I - write and/or read valid in Idle mode P- write and/or read valid in Paused mode S - write and/or read valid in Stop mode E - write and/or read valid in Encode mode All - write and/or read valid in Idle, Encode, Paused and Stop mode. Table 13 I2C-bus control ADR HEX 00 01 02 03 04 05 06 07 all I I, P, S E E I M COMMAND NAME soft reset enable start stop pause(1) sleep R/W W W W W W W W W SIZE/POSITION none none none none none none none none PARAMETER/RANGE none none none none none none none none DEFAULT - - - - - - - - DESCRIPTION This command resets the SAA6752HS to its default settings. go to Stop mode from Idle mode go to Encode mode go to Stop mode from Encode mode go to Paused mode from Encode mode go to Idle mode go to Power-down mode Go to Idle mode without completing the current GOP/audio frame. This is intended for use in cases similar to no video/audio input present. Enables SAA6752HS to time-out to Idle mode if STOP to IDLE transition cannot be completed (i.e. due to no video signal being present). If a general error event is detected, the SAA6752HS will automatically switch to Idle mode via forced reconfigure.
E, P, S reconfigure E, P, S forced reconfigure
08
I
enable system time-out
R/W 1 byte bit 0 = 1 bit 0 = 0 enabled disabled
disabled
SAA6752HS SAA6752HS
Product specification
Note 1. Paused mode transitions are not applicable to transport stream and DIO output mode combination, only transport stream and DEBI output mode combination.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 14 I2C-bus status 2002 Dec 09 2002 Dec 09 40 40 Philips Semiconductors
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
ADR HEX 10 all
M
COMMAND NAME get running mode
R/W R
SIZE/POSITION 1 byte bit 0 = 1 bit 1 = 1 bit 2 = 1 bit 3 = 1 bit 4 = 1 bit 5 = 1 2 bytes (16 bits) bit = 0 bit = 1 2 bytes (16 bits) bit = 0 bit = 1 12 bytes
PARAMETER/RANGE
DEFAULT -
DESCRIPTION This command gets the actual running mode from the SAA6752HS and is read-only. The busy flag indicates that the SAA6752HS is working at a control command. If the busy flag is set, the SAA6752HS skips all received I2C-bus commands.
idle encoding stopped paused reserved busy flag all 0's event disabled event enabled - no event detected event detected - -
11
all
status mask
W
masking of events; see Table 11
12
all
interrupt status
R
This command allows reading a status register. Reading the status will clear the status and reset the interrupt assertion pin. This command allows reading of the current MIPS(R) firmware version number, hardware number and the audio DSP firmware number. Each number contains 4 bytes.
13
all
get version number
R
Table 15 I2C-bus SDRAM size ADR HEX 20 I M COMMAND NAME bus width and memory size R/W SIZE/POSITION PARAMETER/RANGE DEFAULT 16 bit 64 Mbit DESCRIPTION bus width of the SDRAM interface and size of connected SDRAM
R/W 1 byte bit[1:0] = 00 bit[1:0] = 10 bit[1:0] = 11
16 Mbit 16-bit wide 64 Mbit 16-bit wide reserved
SAA6752HS SAA6752HS
Product specification
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MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
ADR HEX 30 I
M
COMMAND NAME clock mode
R/W
SIZE/POSITION
PARAMETER/RANGE
DEFAULT mode 1
DESCRIPTION
R/W 1 byte bit[1:0] = 01 bit[1:0] = 10 bit[1:0] = 11 R/W 1 byte bit 0 = 0 bit 1 = 1 R/W 1 byte bit[1:0] = 00 bit[1:0] = 01 bit[1:0] = 10 mode 1 mode 2 mode 3 crystal clock external clock mode fixed enable mode 2 and 1 auto-switch enable mode 2 and 3 auto-switch
mode 1: crystal frequency fixed; SCR frequency frame locked to V-sync mode 2: crystal frequency frame locked to V-sync mode 3: crystal frequency fixed crystal clock mode fixed This command is used to switch from an internal crystal controlled clock source to an external clock source and vice versa. This command sets the behaviour of the SAA6752HS in Clock mode 2 if video sync cannot be achieved. Either mode 2 is continued or the SAA6752HS will automatically switch to mode 1 or mode 3, as selected. This command outputs the internal crystal generated clock (27 MHz) to an output pin CLKOUT for use in other parts of an application. adjust the frequency of the oscillator
31
I
clock source
32
I
clock auto mode
disable disabled enabled -128 to +127 0
SAA6752HS SAA6752HS
Product specification
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MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
ADR HEX 40 I
M
COMMAND NAME R/W 625/525
SIZE/POSITION
PARAMETER/RANGE
DEFAULT 625
DESCRIPTION defines the input signal either as 625 lines or 525 lines specifies the subsampling type
R/W 1 byte bit[1:0] = 00 bit[1:0] = 01 R/W 1 byte bit[1:0] = 00 bit[1:0] = 01 bit[1:0] = 10 bit[1:0] = 11 R/W 1 byte bit[1:0] = 00
625 525 D1 D1 2/3D1 1/2D1 SIF 0 H-sync, V-sync and Field Identification (FID) information coded in the EAV/SAV bytes complying to ITU-R BT.656 separate H-sync, V-sync and FID signals input to from external source(s) separate H-sync and V-sync signals input to from external source(s) video clock 1 video clock 2 0, 0 0 to 225 0 to 225 0 to 511 (bits 0 to 8) 0 video clock 1
41
I
subsampling type
42
I
video sync format
defines the incoming video sync sources
bit[1:0] = 01
bit[1:0] = 10
R/W 1 byte bit 0 = 0 bit 0 = 1 R/W 2 bytes byte 0 byte 1 R/W 2 bytes
defines which external video input clock is used
defines the number of shifted lines in the top field defines the number of shifted lines in the bottom field defines the number of shifted cycles for every line
SAA6752HS SAA6752HS
Product specification
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MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
M
COMMAND NAME R/W sync polarity
SIZE/POSITION
PARAMETER/RANGE
DEFAULT 000
DESCRIPTION defines the polarity of the sync signals
R/W byte bit 0 = 0 bit 0 = 1 bit 1 = 0 bit 1 = 1 bit 2 = 0 bit 2 = 1
H-sync signal HIGH for horizontal blanking H-sync signal LOW for horizontal blanking V-sync signal HIGH for vertical sync V-sync signal LOW for vertical sync FID signal LOW for first field FID signal HIGH for first field enable forced field toggle 0 If no FID polarity transitions are detected in the input signal, then an internal toggle of FID polarity ensures the encoding of some frames. If no FID polarity transitions are detected in the input signal, then no frames are encoded.
47
I
disable forced field toggle (only for SAA6752HS/V103)
R/W
bit 0 = 0
SAA6752HS SAA6752HS
Product specification
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MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
ADR HEX 50
M
COMMAND NAME
R/W
SIZE/POSITION
PARAMETER/RANGE
DEFAULT off
DESCRIPTION enables or disables noise pre-filter and selects the mode for this filter
I, E, P, noise pre-filter S off/on
R/W 1 byte bit[1:0] = 00 bit[1:0] = 01 bit[1:0] = 10
off median filter average filter 4 x 6 bits; bits 0 to 5 valid 3 x 6 bits; bits 0 to 5 valid
51 52 53
I, E, P, noise pre-filter S coefficients I, E, P, noise pre-filter S thresholds I, E, P, horizontal filter S off/on I, E, P, horizontal filter S coefficients
R/W 4 bytes R/W 3 bytes R/W 1 byte bit 0 = 0 bit 0 = 1 R/W 16 bytes
33H, 20H, defines the filter coefficients for the noise 16H, 0DH pre-filter 10, 15, 20 defines the threshold coefficients for the median filter off enables or disables the horizontal filter by bypassing
off on array of word (8 x 10 bits)
54
first word Defines the coefficients for the horizontal filter; = 256, the the default applies to D1 mode only. When others = 0 other subsampling modes are selected the SAA6752HS automatically overwrites the horizontal filter coefficients with the appropriate parameters. 8 Defines the scaling factor for the horizontal filter; the default applies to D1 mode only. When other subsampling modes are selected the SAA6752HS automatically overwrites the horizontal filter scaling parameter with the appropriate parameter.
SAA6752HS SAA6752HS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 19 I2C-bus video front-end VBI data extraction 2002 Dec 09 2002 Dec 09 45 45 Philips Semiconductors
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
ADR HEX 60 I
M
COMMAND NAME R/W VBI mode select W
SIZE/POSITION 5 bytes bit 0 = 0 bit 0 = 1 bit 8 = 0 bit 8 = 1
PARAMETER/RANGE
DEFAULT -
DESCRIPTION
WSS mode CC mode data input sliced data input unsliced sliced data
selects between WSS and CC modes Selects if the input data is sliced by the video input processor (sliced) or by the SAA6752HS (unsliced). sent in case of sliced input data The data type compared with the data type field in the VBI data header for extraction decision; bits 3 and 2. The SDID compared with the SDID field in the VBI data header for extraction decision. line number of data as set by the video input processor field dependent on video input processor setting The data type compared with the data type field in the VBI data header for extraction decision; bits 1 and 0. match the SDID match data type match field match line number must be set to zero
bit[17:16]
data type[3:2]
bit[23:18] bit[28:24] bit 29 = 0 bit 29 = 1 bit[31:30]
SDID, 0 to 63 line number, 0 to 31 top field bottom field data type[1:0]
bit 32 = 1 bit 33 = 1 bit 34 = 1 bit 35 = 1 bit[39:36]
field qualifier mask SDID field qualifier mask data type field qualifier mask field field qualifier mask line number reserved
SAA6752HS SAA6752HS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Dec 09 2002 Dec 09 46 46 63 I CC data enable 64 all CC read data R Philips Semiconductors ADR HEX 60 I
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
M
COMMAND NAME R/W VBI mode select (continued) W
SIZE/POSITION continued bit[20:16] bit[28:24] bit[37:32] bit 38 = 1 bit 39 = 1
PARAMETER/RANGE unsliced data line number for bottom, 0 to 31 line number for top, 0 to 31 reserved field qualifier mask line field 1 field qualifier mask line field 2
DEFAULT -
DESCRIPTION sent in case of unsliced input data line number for bottom field as set by the video input line number for top field as set by the video input must be set to zero match if field = `top' and line = `line number' match if field = `bottom' and line = `line number'
61
I
WSS data enable
R/W 1 byte bit[1:0] = 00 bit[1:0] = 01 bit[1:0] = 10
disabled disabled enabled enabled without checksum - WSS data valid data invalid or previous data disabled disabled enabled - CC data top field bottom field valid data invalid data -
enables or disables WSS data extraction
62
all
WSS read data
R/W 2 bytes bit[13:0] bit 15 = 0 bit 15 = 1 R/W 1 byte bit 0 = 0 bit 0 = 1 3 bytes bit[15:0] bit 16 = 0 bit 16 = 1 bit 23 = 0 bit 23 = 1
WSS data and flag indicating valid data
enables the closed caption data extraction
CC data and flags indicating valid data and current field
SAA6752HS SAA6752HS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Dec 09 2002 Dec 09 47 47 bit 4 = 0 bit 4 = 1 bit 5 = 0 bit 5 = 1 bit 6 bit 7 Philips Semiconductors ADR HEX 65 I
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
M
COMMAND NAME R/W user data insertion mode (only for SAA6752HS/V103)
SIZE/POSITION
PARAMETER/RANGE
DEFAULT 00H
DESCRIPTION selects the user data insertion mode external user data insertion into GOP header (user data 1) external user data insertion into picture header (user data 2) Internal user data insertion of Closed Caption data into GOP header user data area according to DVD standard. Note: Only one internal user data insertion mode can be active at the same time, either bit 2 = 1 or bit 3 = 1 Internal user data insertion of Closed Caption data into picture header user data area according to ATSC/NTSC standard. Note: Only one internal user data insertion mode can be active at the same time, either bit 2 = 1 or bit 3 = 1 Stop user data insertion into GOP header user data area. This bit can be used in all operation modes. Setting this bit to logic 1 (= stop) deletes the downloaded GOP user data and resets bit 2 to `disabled' Stop user data insertion into picture header user data area. This bit can be used in all operation modes. Setting this bit to logic 1 (= stop) deletes the downloaded picture user data and resets bit 3 to `disabled' must be set to zero must be set to zero
R/W 1 byte bit 0 = 0 bit 0 = 1 bit 1 = 0 bit 1 = 1 bit 2 = 0 bit 2 = 1 always repeated only once always repeated only once disabled enabled
bit 3 = 0 bit 3 = 1
disabled enabled
- stop
- stop
reserved reserved
SAA6752HS SAA6752HS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 20 I2C-bus video encoder: general 2002 Dec 09 2002 Dec 09 48 48 74 75 Philips Semiconductors
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
ADR HEX 70 I
M
COMMAND NAME R/W disable video encoder
SIZE/POSITION
PARAMETER/RANGE
DEFAULT enabled
DESCRIPTION Specifies if the video encoder is enabled. If the video encoder is disabled, no video data will be inserted in the output stream. defines the encoding bit rate control mode (variable or constant bit rate)
R/W 1 byte bit 0 = 0 bit 0 = 1 R/W 1 byte bit 0 = 0 bit 0 = 1 VBR CBR distance (M) (0 to 3) length (N) (0 to 19) enabled disabled
71
I
bit rate mode
VBR
72
I
GOP definition
R/W 2 bytes byte 0 byte 1
0001H: M = 0; N=1
Defines the used GOP structure as (N.M), where `N' is the number of frames per GOP and `M' is the distance of 2 sequential I- or P-frames (reference frame distance); distance = 0 is I-frame coding; see Table 3 for meaningful combinations. Specifies the data to be inserted into the GOP header.
73
I
user data GOP header
R/W 64 bytes
all 0
E, P, S user data GOP header (only for SAA6752HS/V103) I number of user data R/W 1 byte GOP 0 Specifies the amount of user data to be inserted into the GOP header.
E, P, S number of user data GOP (only for SAA6752HS/V103) I number of user data R/W 1 byte picture header 0 Specifies the amount of user data to be inserted into the picture header.
E, P, S number of user data picture header (only for SAA6752HS/V103)
SAA6752HS SAA6752HS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Dec 09 2002 Dec 09 49 49 7A 7B I I reserved - - disable forced R/W 1 byte backward prediction bit 0 = 0 bit 0 = 1 7C I scan select R/W 1 byte bit 0 = 0 bit 0 = 1 alternate scan zigzag scan Philips Semiconductors ADR HEX 76 I
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
M
COMMAND NAME R/W user data picture header
SIZE/POSITION
PARAMETER/RANGE
DEFAULT all 0
DESCRIPTION Specifies the data to be inserted into the picture header. If internal user data insertion of Closed Caption data into the GOP header is active and the GOP size is larger than 9, then the insertion of user data to the picture header is not available.
R/W 64 bytes
E, P, S user data picture header (only for SAA6752HS/V103)
77
I
noise filter coefficients
R/W 2 bytes byte 0 byte 1 gain criterion
off
Defines the noise filter coefficients gain and criterion scale.
E, P, S noise filter coefficients (only for SAA6752HS/V103) 78 I adaptive quantization depth quantizer matrix
R/W 1 byte
0 to 128
32
Selects the depth of quantization adaptation; 0 for no adaptation, 128 for maximum adaptation. Specifies the quantizer matrix as 2 tables, each an 8 x 8 array. Data must be transferred column by column, not row by row. The inter Q matrix must be downloaded first, the intra Q matrix downloaded second; see note 1. - Applies only for GOP structures starting with a B-frame: disabled forced backward prediction results in non-editable (open) GOPs with prediction from a former GOP. Enabled forced backward prediction results in backward predicted closed GOPs without prediction from a former GOP. In all cases the leading B-frames of the very first GOP structure after start of encoding are forced to backward prediction.
79
I
R/W 2 x 64 bytes
array of integers (8 x 8 bytes)
-
- enabled disabled
- 0
SAA6752HS SAA6752HS
Product specification
0
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Dec 09 2002 Dec 09 50 50 Philips Semiconductors ADR HEX 7D I
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
M
COMMAND NAME R/W quantizer scale table
SIZE/POSITION
PARAMETER/RANGE
DEFAULT 0
DESCRIPTION
R/W 1 byte bit 0 = 0 bit 0 = 1 logarithmic linear
Note 1. If no Q matrix is downloaded then the default is the MPEG standard and no Q matrix is inserted into the stream. Table 21 I2C-bus video encoder: bit rate control (dynamic settings) ADR HEX 80 M COMMAND NAME R/W SIZE/POSITION - PARAMETER/RANGE DEFAULT 6000 DESCRIPTION VBR target bit rate (kbit/s); this applies to VBR mode only; Rvbr must be set to less than Rmax. CBR mode: target bit rate (kbit/s); VBR mode: maximum bit rate (kbit/s); note 1. Minimum Q-scale for external constraints of VBR Maximum Q-scale for external constraints of VBR. B-frame weighting factor (internally divided by 128; i.e. 128 = no effect) This command reads the number of bytes per GOP.
I, E, P, Rvbr S I, E, P, Rmax S I, E, P, Qmin_VBR S I, E, P, Qmax_VBR S I, E, P, B-frame weighting S
R/W 2 bytes
81
R/W 2 bytes
-
9800
82 83 84 85 Note
R/W 1 byte R/W 1 byte R/W 1 byte 4 bytes
1 to 112 1 to 112 32 to 128 -
4 12 128, no weighting -
I, E, P, read bytes per GOP R S
1. If the video bit rate Rmax is intended to be changed during the encoding state, the maximum applied value for Rmax has to be set before start of encoding. I.e. the Rmax value that was valid at start of encoding (coming from stop) is the maximum allowed value for this encoding process.
SAA6752HS SAA6752HS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 22 I2C-bus audio encoder: bit rate control (static settings) 2002 Dec 09 2002 Dec 09 51 51 92 I audio input mode and port select R/W 1 byte bit 0 = 0 bit 0 = 1 bit 1 = 0 bit 1 = 1 93 I audio processing mode R/W 1 byte bit[1:0] = 00 bit[1:0] = 01 MPEG-1 L2 encode DDC encode (only for SAA6752HS/V101 and SAA6752HS/V103) LPCM bypass DVD bypass master mode slave mode port 1 port 2 MPEG-1 L2 bit[1:0] = 10 bit[1:0] = 11 Philips Semiconductors
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
ADR HEX 90 I
M
COMMAND NAME disable audio encoder
R/W
SIZE/POSITION
PARAMETER/RANGE
DEFAULT 0
DESCRIPTION Specifies if the audio encoder is enabled. If the audio encoder is disabled, no audio data will be inserted in the output stream. defines the audio input format
R/W 1 byte bit 0 = 0 bit 0 = 1 enabled disabled
91
I
audio input format R/W 1 byte bit[2:0] = 000 bit[2:0] = 001 bit[2:0] = 010 bit[2:0] = 011 bit[2:0] = 100 bit[2:0] = 101 bit[2:0] = 110 bit[2:0] = 111 I2S reserved EIAJ 16 bits EIAJ 18 bits EIAJ 20 bits EIAJ alternative format 16 bits EIAJ alternative format 18 bits EIAJ alternative format 20 bits
I2S
slave, port 1
In master mode, SAA6752HS delivers the bit clock and word select signal. In slave mode, SAA6752HS receives the bit clock and word select signal. Note that, if I2S port 2 is switched to output mode (VES + AES output stream mode) then SAA6752HS is fixed to master mode. defines the audio processing mode (see Section 7.5); note 1
SAA6752HS SAA6752HS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Dec 09 2002 Dec 09 52 52 Philips Semiconductors ADR HEX 94 I M COMMAND NAME
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
R/W
SIZE/POSITION
PARAMETER/RANGE
DEFAULT
DESCRIPTION
audio encoding R/W 1 byte bit rate and output bit 0 = 0 resolution bit 0 = 1 bit 1 = 0 bit 1 = 1
256 kbit/s 384 kbit/s 16-bit reserved 256 x 48 kHz 384 x 48 kHz
256 kbit/s defines the audio encoding bit rate (see 16-bit Section 7.5); note 2
95
I
audio clock output R/W 1 byte frequency bit 0 = 0 bit 0 = 1 audio pre-emphasis mode R/W 1 byte bit[1:0] = 00 bit[1:0] = 01 bit[1:0] = 10
256 x 48 kHz
selects the output frequency at the audio clock mode
96
I
off off 50/15 ms CCITT J17
selects audio pre-emphasis mode of input signal (valid for MPEG encoding only)
Notes 1. In systems that use 16 Mbit SDRAM, due to system architecture constraints, LPCM bypass must be restricted to be used with I and IP video encoding only. There is no constraint if 64 Mbit SDRAM is used. 2. All compressed audio data is 16-bit. In the event of LPCM bypass 20-bit data will be truncated to 16 bits.
SAA6752HS SAA6752HS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 23 I2C-bus audio encoder: bit rate control (dynamic settings) 2002 Dec 09 2002 Dec 09 53 53 Philips Semiconductors
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
ADR HEX A0
M
COMMAND NAME
R/W R
SIZE/POSITION 1 byte bit[4:0] bit[6:5] bit 7
PARAMETER/RANGE
DEFAULT I2S
DESCRIPTION Preamble Pc in case of IEC 61937 input (data type), applies to DVD bypass mode only
E, P, S Preamble Pc
data type reserved error flag indicating validity of burst load Preamble Pd (16 bits) -
A1
E, P, S Preamble Pd
R
2 bytes
Preamble Pd in case of IEC 61937 input (payload length); this applies to DVD bypass mode only Part of audio frame header in case of IEC 61937 input; this applies to DVD bypass mode only. -
A2
E, P, S audio bit stream information - all reserved audio mute on/off
R
8 bytes
bit stream information (4 x 16 bits) -
-
A3 A4
-
- bit 0 = 0 bit 0 = 1
- 0
R/W 1 byte off on
SAA6752HS SAA6752HS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 24 I2C-bus multiplexer: general (static settings) 2002 Dec 09 2002 Dec 09 54 54 B1 I maximum system bit rate B2 I number of flushing bytes Philips Semiconductors
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
ADR HEX B0 I
M
COMMAND NAME output stream format
R/W
SIZE/POSITION
PARAMETER/RANGE
DEFAULT
DESCRIPTION
R/W 1 byte bit[2:0] = 000 bit[2:0] = 001 bit[2:0] = 010 bit[2:0] = 011 ES video (VES) ES audio (AES) PES (DVD) PES (TS)
PS (DVD) Selects the MPEG-2 output format (see SAA6752HS output stream formats for details): Elementary Stream (ES): Elementary stream output is possible for audio or video only encoding. Packetized Elementary Stream (PES): DVD-compliant: PES packets have a limited size and can be easily multiplexed into a DVD program stream. TS-compliant: PES packets have an unlimited size and can be easily multiplexed into a transport stream. PES packets containing audio and video information are flagged with an audio/video signal pin. The audio/video polarity of the signal pin is programmable. Program Stream (PS): A DVD-compliant program stream is generated, but no navigation packs are inserted. Transport Stream (TS): A transport stream is generated. Pack stream is a special not MPEG-compliant mode. The MPEG buffer model is not used. VES + AES mode allows VES output from the output port at the same time as an SPDIF formatted AES is output from the 2nd I2S audio port. For this mode subaddress 92H must be set to zero. 10800 Maximum target bit rate of the system stream in kbit/s (= 1000 bit/s) and must be set if TS or PS or pack stream modes are selected. It is ignored if ES or PES streams are selected. Number of flushing bytes appended to the stream after a stop.
bit[2:0] = 100
PS (DVD)
bit[2:0] = 101 bit[2:0] = 110 bit[2:0] = 111
TS pack stream VES + AES
R/W 2 bytes
<27000; note 1
SAA6752HS SAA6752HS
Product specification
R/W 2 bytes
-
0
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Dec 09 2002 Dec 09 55 55 bit 7 = 0 bit 7 = 1 B7 B8 I E audio substream R/W 1 byte ID current system bit rate R 2 bytes B9 I enable MPEG end code R/W 1 byte bit 0 = 1 bit 0 = 0 enable disable Philips Semiconductors ADR HEX B3 B4 B5 I I I M COMMAND NAME video PES ID audio PES ID PES original copy and copyright
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
R/W
SIZE/POSITION
PARAMETER/RANGE E0H to EFH C0H to DFH
DEFAULT E0H C0H copy, no copyright
DESCRIPTION Stream ID for video PES header; must be set for TS, PS and PES output. Stream ID for audio PES header; must be set for TS, PS and PES output. Copy and copyright setting in audio and video PES header.
R/W 8 bits R/W 8 bits R/W 1 byte bit 0 = 0 bit 0 = 1 bit 1 = 0 bit 1 = 1
original copy copyright no copyright 1 to 15, number of GOP/VOBU metabyte output off metabyte output on 0 to 3, time slot reservation for NAV packets inserted not inserted
B6
I
multiplexer special DVD PS settings
R/W 1 byte bit[3:0] bit 4 = 0 bit 4 = 1 bit[6:5]
2 GOPs, off, metabyte, 0 (NAV packet), inserted (PES header)
The number of GOPs per VOBU for PS output. Enables/disables the output of metabytes for PS (DVD) and pack stream modes. Specifies the number of reserved time slots for navigation packets and DVD recorder data. Determines if the PES header extension is inserted into the stream; this applies to program stream and pack stream modes; note: for DVD-compliance, the PES header extension must be inserted
- -
00 -
audio substream ID; for PS (DVD) or PES (DVD) only Current system bit rate of the system stream in kbit/s (= 1000 bit/s); applies for PS and TS modes. The parameter includes the number of stuffing bytes. During pause mode, this address will read back the value of the last GOP before the pause command. Enables the MPEG end code (for program stream only).
SAA6752HS SAA6752HS
Product specification
disable
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Note 2002 Dec 09 2002 Dec 09 56 56 C3 I TS miscellaneous R/W 1 byte bit 0 = 0 bit 0 = 1 bit 1 = 0 DIT insertion disabled DIT insertion enabled constant TS bit rate 00H bit 1 = 1 variable TS bit rate (only for SAA6752HS/V103) C4 I clock TS packet ID R/W 2 bytes 0020H to 1FFEH 0104H Philips Semiconductors
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
1. The limit for I-frame only is 27 Mbit/s. For IP or IPB formats the limit is 16 Mbit/s. Table 25 I2C-bus multiplexer: transport stream (static settings) ADR HEX C0 C1 C2 I I I M COMMAND NAME video TS packet ID audio TS packet ID system information tables R/W SIZE/POSITION PARAMETER/RANGE 0020H to 1FFEH 0020H to 1FFEH first byte is table number range (0 to 4) + array of maximum 188 bytes values DEFAULT 0100H 0102H - DESCRIPTION Packet ID for transport stream packets containing video data; for TS only. Packet ID for transport stream packets containing audio data; for TS only. There are 5 different tables followed by an array of up to 188 bytes.The tables must be sent one by one; the size of the tables is not defined but limited to 188 bytes. Table 0: Program Association Table (PAT) Table 1: Program Map Table (PMT) Table 2: free programmable [e.g. Conditional Access Table (CAT)] Table 3: free programmable [e.g. Network Information Table (NIT)] Table 4: free programmable [e.g. Selection Information Table (SIT)] A discontinuity information table is inserted at the beginning of the stream (after a stop of recording). At constant TS bit rate mode null packets are delivered at the multiplexer output to achieve the constant TS bit rate. At variable TS bit rate mode no null packets are inserted at the multiplexer output. This mode can be used in combination with variable video bit rate (only for SAA6752HS/V103). Packet ID for transport stream packets containing PCR values; for TS only.
R/W 2 bytes R/W 2 bytes W 189 bytes (maximum value); up to 5 separate tables
SAA6752HS SAA6752HS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 26 I2C-bus output interface 2002 Dec 09 2002 Dec 09 57 57 sync pin polarity data request pin polarity PDO clock frequency F6 I insert leading null bytes (only for SAA6752HS/V103) W bit 5 = 0 bit 5 = 1 bit 6 = 0 bit 6 = 1 bit 7 = 0 bit 7 = 1 2 bytes positive negative negative positive 9 MHz 6.75 MHz number of bytes 00H 9 MHz selection of clock frequency for DIO master mode Defines the number of leading null bytes (00H), which are delivered to the output before the start of the stream; note: after forced reconfigure command the default value of 00H will be set. negative Philips Semiconductors
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer audio encoder with multiplexer
ADR HEX D0 I
M
COMMAND NAME R/W
SIZE/POSITION
PARAMETER/RANGE
DEFAULT
DESCRIPTION Defines the output interface in one byte (collects all sub parameter bits in one byte). All states defined are the active states
R/W 1 byte
output protocol
bit[1:0] = 00 bit[1:0] = 01 bit[1:0] = 10 bit[1:0] = 11
DIO slave mode DIO master mode not applicable DEBI slave mode positive negative off on audio HIGH, video LOW audio LOW, video HIGH
DIO slave DIO master mode: SAA6752HS delivers the mode clock signal. DIO slave mode: SAA6752HS receives the clock signal. positive on audio HIGH, video LOW positive must be negative if DEBI mode is selected Selection of high-impedance for output pin.
data valid pin polarity high impedance on/off audio/video pin polarity
bit 2 = 0 bit 2 = 1 bit 3 = 0 bit 3 = 1 bit 4 = 0 bit 4 = 1
SAA6752HS SAA6752HS
Product specification
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDP VDDCO VDDA VI Vi VO Isc Ilu(prot) Ptot Tstg Tamb Ves PARAMETER digital supply voltage for pads digital supply voltage for core analog supply voltage digital input voltage analog input voltage digital output voltage short-circuit current of output pads latch-up protection current total power dissipation storage temperature ambient temperature electrostatic handling voltage note 5 note 6 Notes 1. All pads are not 5 V tolerant. 2. Pins XTALI and XTALO. 3. At VDDP > 3.7 V only maximum 4.2 V at digital outputs is allowed. 4. Short-circuit current is only allowed for a short time (<1 s). 5. Human body model: C = 100 pF; R = 1.5 k. 6. Machine model: C = 200 pF; L = 0.75 H; R = 0 . 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS note 1 note 2 note 3 note 4 CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 - - - -25 0 -2000 -150
SAA6752HS
MAX. +4.0 +2.8 +2.8 +4.0 +2.8 125 100 2 +125 70 +2000 +150 V V V V V
UNIT
VDDP + 0.5 V mA mA W C C V V
VALUE 28
UNIT K/W
thermal resistance from junction to ambient in free air; soldered to a PCB with supply and ground plane
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SAA6752HS
12 CHARACTERISTICS VDDCO = 2.5 V, VDDA = 2.5 V and VDDP = 3.3 V for the I/O pads; supply voltages VDDCO and VDDA are connected externally together; grounds VSSCO, VSSA and VSSP are connected externally together; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies: pins VDDP, VDDCO and VDDA VDDP VDDCO VDDA IDDP IDDCO IDDA Ptot VIL VIH Vhys IIL IIH CI VIL VIH Vhys Ipu(L) Ipu(H) CI VIL VIH Vhys Ipd CI digital supply voltage (pad cells) digital supply voltage (core) analog supply voltage (oscillator and PLL) digital supply current (pad cells) digital supply current (core) analog supply current total power dissipation 3.0 2.3 2.3 17 390 - 0.95 -0.5 1.7 0.4 VIL = VSSP VIH = VDDP -5 - - -0.5 1.7 0.4 VIL = VSSP -20 3.3 2.5 2.5 25 430 3 1.16 - - - - - - - - - -50 0 - - - - -50 - 3.6 2.7 2.7 37 500 - 1.48 V V V mA mA mA W
Input: pins YUV0 to YUV7 LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level input current HIGH-level input current input capacitance +0.7 VDDP - - 5 10 V V V A A pF
Input with pull-up resistor: pins CTS, EXTCLK, I2CADDRSEL, PDIDS, RESET, RXD, TCK, TDI, TMS and TRST LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level pull-up input current HIGH-level pull-up input current input capacitance +0.7 VDDP - -70 10 10 V V V A A pF
VDDCO < VIH < VDDP - - -0.5 1.7 0.4 VDDCO < VIL < VDDP -20 -
Input with pull-down resistor: pins FID, IDQ, HSYNC, SDATA1, VCLK1, VCLK2 and VSYNC LOW-level input voltage HIGH-level input voltage hysteresis voltage pull-down input current input capacitance +0.7 VDDP - -70 10 V V V A pF
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SYMBOL PARAMETER CONDITIONS -0.5 1.7 0.4 - VDDP - 0.4 -55 -5 - - IOH = -4 mA note 1 VIH = VDDP; VIL = VSSP MIN. - - - - - - - - - TYP.
SAA6752HS
MAX.
UNIT
Inputs/outputs with Imax = 4 mA: pins PDIOCLK, SM_CS0, SM_LB, SM_UB, TEST0, TEST1 and TEST2 VIL VIH Vhys VOL VOH Isc ITL CI CL LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage IOL = 4 mA HIGH-level output voltage short-circuit current 3-state leakage current input capacitance load capacitance +0.7 VDDP - 0.4 VDDP +55 +5 10 30 V V V V V mA A pF pF
Inputs/outputs with Imax = 4 mA and pull-down resistor: pins SCLK1, SCLK2, SDATA2, SM_D0 to SM_D15, SWS1 and SWS2; note 2 VIL VIH Vhys VOL VOH Isc Ipd CI CL LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage IOL = 4 mA HIGH-level output voltage short-circuit current pull-down input current input capacitance load capacitance IOH = -4 mA note 1 -0.5 1.7 0.4 - VDDP - 0.4 -55 - - -0.5 1.7 0.4 - VDDP - 0.4 -55 -5 - - IOH = -8 mA note 1 VIH = VDDP; VIL = VSSP - - - - - - -50 - - - - - - - - - - - +0.7 VDDP - 0.4 VDDP +55 -70 10 30 V V V V V mA A pF pF
VDDCO < VIL < VDDP -20
Inputs/outputs with Imax = 8 mA: pins SD_DQ0 to SD_DQ31; note 2 VIL VIH Vhys VOL VOH Isc ITL CI CL LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage IOL = 8 mA HIGH-level output voltage short-circuit current 3-state leakage current input capacitance load capacitance +0.7 VDDP - 0.4 VDDP +55 +5 10 30 V V V V V mA A pF pF
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SYMBOL PARAMETER CONDITIONS - VDDP - 0.4 -55 -1 - - VDDP - 0.4 -55 -20 MIN. - - - - - - - - -50 0 - TYP.
SAA6752HS
MAX.
UNIT
3-state output with Imax = 4 mA: pins PDO0 to PDO7, PDOAV and PDOSYNC; note 2 VOL VOH Isc ITL CL LOW-level output voltage IOL = 4 mA HIGH-level output voltage short-circuit current 3-state leakage current load capacitance IOH = -4 mA note 1 VIH = VDDP; VIL = VSSP 0.4 VDDP +55 +1 30 V V mA A pF
3-state output with Imax = 4 mA and pull-up resistor: pin PDOVAL; note 2 VOL VOH Isc Ipu(L) Ipu(H) CL LOW-level output voltage IOL = 4 mA HIGH-level output voltage short-circuit current LOW-level pull-up input current HIGH-level pull-up input current load capacitance IOH = -4 mA note 1 VIL = VSSP 0.4 VDDP +55 -70 10 30 V V V A A pF
VDDCO < VIH < VDDP - -
Output with Imax = 4 mA: pins ACLK, CLKOUT, RTS, SM_A0 to SM_A17, SM_CS3, SM_OE, SM_WE, TDO and TXD VOL VOH Isc ITL CL LOW-level output voltage IOL = 4 mA HIGH-level output voltage short-circuit current 3-state leakage current load capacitance IOH = -4 mA note 1 VIH = VDDP; VIL = VSSP - VDDP - 0.4 -55 -1 - - - - - - 0.4 VDDP +55 +1 30 V V mA A pF
Output with Imax = 8 mA: pins SD_A0 to SD_A13, SD_CAS, SD_CKE, SD_CLK, SD_CS, SD_DQM0 to SD_DQM3, SD_RAS and SD_WE VOL VOH Isc CL LOW-level output voltage IOL = 8 mA HIGH-level output voltage short-circuit current load capacitance IOH = -8 mA note 1 - VDDP - 0.4 -125 - - - - - - - - - 0.4 VDDP +125 30 V V mA pF
I2C-bus interface: pins SCL and SDA; notes 3 and 4 fSCL VIL VIH Vhys II SCL clock frequency LOW-level input voltage HIGH-level input voltage hysteresis voltage input current 100 - 0.7VDDP - -10 400 0.3VDDP 3.6 +10 kHz V V V A
0.05VDDP -
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SYMBOL VOL tLOW tHIGH tr(I2C) tf(I2C) tSU;DAT tHD;STA tSU;STO PARAMETER LOW-level output voltage; open-drain SCL LOW time SCL HIGH time rise time of both SDA and SCL fall time of both SDA and SCL data set-up time hold time START condition set-up time STOP condition CONDITIONS 3 mA sink current 0 1.3 0.6 - - 100 0.6 0.6 MIN. - - - - - - - - TYP.
SAA6752HS
MAX. 0.4 - - 0.3 0.3 - - -
UNIT V s s s s ns s s
Video clock input timing: pins VCLK1 and VCLK2; see Fig.15 Tcy tr(VCLK) tf(VCLK) tSU;DAT tHD;DAT fi(D) fH fV cycle time duty factor rise time fall time tHIGH/Tcy VI = 0.8 to 2 V VI = 2 to 0.8 V 35 40 - - 6 3 37 50 - - - - 27 15625 15734 50 60 288 240 39 60 5 6 - - 28.54 16515 16631 50.75 60.9 311 259 ns % ns ns
Video input data and control timing: pins YUV7 to YUV0, FID, HSYNC and VSYNC; see Fig.15 data set-up time data hold time ns ns
Video input parameter range data input frequency rate frame-locked; notes 5 and 6 line frequency field frequency 625 lines; note 6 525 lines; note 6 625 lines; notes 7 and 8 525 lines; notes 7 and 8 Nal/f active lines/field 625 lines; notes 7 and 9 525 lines; notes 7 and 9 Crystal oscillator: pins XTALI and XTALO; note 10 fXTAL fstab CL VIL fundamental frequency MPEG2 frequency stability load capacitance LOW-level input voltage note 11 note 11 27 x 27 (1 - 80 x 10-6) 27 x - (1 - 30 x 10-6) 8 if used with external -0.5 clock 10 - 27 x MHz (1 + 80 x 10-6) 27 x MHz (1 + 30 x 10-6) 12 +0.7 pF V 25.46 14734 14837 46 55 265 221 MHz kHz kHz kHz kHz
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SYMBOL VIH Cshunt Rs Ntune Ctune(min) Ctune(max) fstep PARAMETER HIGH-level input voltage shunt capacitance serial resistance CONDITIONS if used with external 1.7 clock - - -127 Ntune = 128 Ntune = -127 - - 14 MIN. - - - - 8 72 42 TYP.
SAA6752HS
MAX. VDDA 7 25
UNIT V pF
Crystal oscillator tuning: pins XTALI and XTALO; note 10 tuning steps minimum internal tuning capacitance to VSSA maximum internal tuning capacitance crystal frequency offset per tuning step +128 - - 70 pF pF Hz
External clock input: pin EXTCLK fEXTCLK tr(EXTCLK) tf(EXTCLK) I2C-bus VIL external frequency duty factor rise time fall time square wave; note 11 tHIGH/Tcy VI = 0.7 to 1.7 V VI = 1.7 to 0.7 V 25.7 40 - - -0.5 27.0 50 - - - 28.3 60 5 6 MHz % ns ns
address select input: pin I2CADDRSEL LOW-level input voltage for I2C-bus addresses 40H and 41H HIGH-level input voltage for I2C-bus addresses 42H and 43H +0.7 V
VIH
1.7
-
VDDP
V
Reset input: pin RESET VIL tstart tlength LOW-level input voltage for active reset start time of first reset pulse after power-on length of reset pulse after power-on and after sleep initialization phase after reset pulse until I2C-bus commands are accepted -0.5 - 10 - 0 - +0.7 10 - V s ms
tinit
-
-
1
s
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA6752HS
MAX.
UNIT
SDRAM interface data, address and control timing: pins SD_DQ31 to SD_DQ0, SD_A13 to SD_A0, SD_CAS, SD_RAS, SD_WE and SD_OE Tcy tCAS tRCD tRRD tRP tWR tRSC tRAS tRC tpower-up td(C-D) cycle time CAS latency time row to column delay time activate to activate delay time row precharge time write recovery time mode register set cycle time row activate time row cycle time wait time after power-on clock to data output delay clock to address output delay data input set-up time data input hold time CL(SD_CLK) = 15 pF; CL(SD_DQn) = 8 pF; fSD_CLK = 108 MHz CL(SD_CLK) = 15 pF; CL(SD_An) = 8 pF; fSD_CLK = 108 MHz fsys = 27 MHz - - - - - - - - - 500 2.5 9.26 3 3Tcy 2Tcy 3Tcy 2Tcy 2Tcy 6Tcy 8Tcy 515 4.0 - - - - - - - - - - 5.0 ns clock cycles ns ns ns ns ns ns ns s ns
td(C-A)
2.5
4.0
5.0
ns
tsu(D) th(D) tl-o(PDIDS-PDOVAL) tl-o(PDIDS-PDO) tstab(PDO-PDOVAL) tr(PDOVAL-PDO)
1 2.5
- - - - - -
- - 20 20 - -
ns ns
Data output interface timing: pins PDO7 to PDO0, PDIDS, PDOSYNC, PDOAV and PDIOCLK PDIDS to PDOVAL low-ohmic time PDIDS to PDO[7:0] low-ohmic time PDO[7:0] data stable to falling PDOVAL time rising PDOVAL to PDO[7:0] high-impedance time PDO[7:0] data to PDIOCLK hold time PDO[7:0] data to PDIOCLK set-up time input PDIOCLK HIGH time input PDIOCLK LOW time DEBI slave mode DEBI slave mode DEBI slave mode DEBI slave mode 0 0 10 10 ns ns ns ns
th(PDO-PDIOCLK) tsu(PDO-PDIOCLK) ti(PDIOCLK)H ti(PDIOCLK)L
DIO master mode; PDOVAL = 1 DIO master mode; PDOVAL = 1 DIO slave mode DIO slave mode DIO slave mode; PDOVAL = 1
10 10 55 55 36
- - - - -
- - - - 58
ns ns ns ns ns
tstab(PDIOCLK-PDO) falling input PDIOCLK to PDO[7:0] data stable time 2002 Dec 09
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
Notes 1. Short-circuit current is only allowed for a short time (<1 s). 2. The output pins are 3.3 V tolerant when in 3-state mode.
SAA6752HS
3. Pins SCL and SDA of the I2C-bus interface do not obstruct the SDA and SCL lines if the supply voltage VDDP is switched off. 4. The open-drain outputs are 3.3 V tolerant. 5. Frame-locked input data rate deviation from SAA6752HS crystal clock. 6. Supporting output range of the Philips SAA7114 video input processor. 7. Applies for line frequencies 2% from nominal. 8. Minimum limit according to IEC 60756; maximum limit because the SAA6752HS may drop frames for V-sync frequencies greater than 1.5% above nominal. 9. Deviation according to IEC 60756.7. The SAA6752HS will only encode 240 lines (when in 525-line mode) and 288 lines (when in 625-line mode). Therefore any additional lines in a field above these values will not be encoded. 10. Pin XTALO has to be used for connection with a crystal only. Do not use for other purposes. 11. The required stability of the crystal frequency or external system clock is dependent upon the clock mode used in the application.
handbook, full pagewidth
Tcy t HIGH t LOW 1.7 V 1.3 V 0.7 V t HD;DAT t SU;DAT t f(VCLK) t r(VCLK)
VCLK
data and control inputs
1.7 V valid not valid valid 0.7 V
t OH;DAT data and control outputs 2.4 V valid not valid valid 0.4 V
MHC142
Fig.15 Clock data timing.
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
13 PACKAGE OUTLINE SQFP208: plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height
SAA6752HS
SOT316-1
c
y
X
A
156 157 105 104
ZE
e E HE A2 A1 (A 3) Lp L pin 1 index
208 53 52
A
wM bp
detail X
1
e
bp D HD
wM
ZD B
vM A
vM B
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT316-1 REFERENCES IEC JEDEC MS-029 EIAJ EUROPEAN PROJECTION A max. 4.10 A1 0.50 0.25 A2 3.6 3.2 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.5 HD 30.9 30.3 HE 30.9 30.3 L 1.3 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.39 1.11 1.39 1.11 8 0o
o
ISSUE DATE 99-12-27 00-01-25
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
14 SOLDERING 14.1 Introduction to soldering surface mount packages
SAA6752HS
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
14.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
SAA6752HS
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Dec 09
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
15 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
SAA6752HS
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 17 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
ICs with MPEG-audio/AC-3 audio functionality Purchase of a Philips IC with an MPEG-audio and/or AC-3 audio functionality does not convey an implied license under any patent right to use this IC in any MPEG-audio or AC-3 audio application. For more information please contact the nearest Philips Semiconductors sales office or e-mail: licensing.cip@philips.com. 18 PURCHASE OF PHILIPS I2C COMPONENTS
SAA6752HS
ICs with MPEG-2 functionality Use of this product in any manner that complies with the MPEG-2 Standard is expressly prohibited without a license under applicable patents in the MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C., 250 Steele Street, Suite 300, Denver, Colorado 80206.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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70
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
NOTES
SAA6752HS
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/02/pp72
Date of release: 2002
Dec 09
Document order number:
9397 750 10297

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